16
Data Sheet
2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash
SST49LF002B / SST49LF003B / SST49LF004B
2005 Silicon Storage Technology, Inc.
S71232-05-000
1/05
LPC Memory Read Cycle
FIGURE 8: LPC MEMORY READ CYCLE WAVEFORM
TABLE
7: LPC MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]1
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction
Comments
1
START
0000
IN
LFRAME# must be active (low) for the device to respond. Only
the last field latched before LFRAME# transitions high will be
recognized. The START field contents (0000b) indicate an LPC
Memory cycle.
2
CYCTYPE
+ DIR
010X
IN
Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is
reserved.
3-10
ADDR
YYYY
IN
Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
11
TAR0
1111
IN
then Float
In this clock cycle, the host drives the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float
then OUT
The SST49LF00xB takes control of the bus during this cycle.
13
SYNC
0000
OUT
The SST49LF00xB outputs the value 0000b indicating that it
has received data.
14
DATA
ZZZZ
OUT
ZZZZ is the least-significant nibble of the data byte.
15
DATA
ZZZZ
OUT
ZZZZ is the most-significant nibble of the data byte.
16
TAR0
1111
IN
then Float
In this clock cycle, the host drives the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float
then OUT
The SST49LF00xB takes control of the bus during this cycle.
T7.0 1232
1232 F05.1
LCLK
LFRAME#
LAD[3:0]
0000b
010Xb
A[23:20] A[19:16]
A[3:0]
A[7:4]
A[11:8]
A[15:12]
1111b
Tri-State
2 Clocks
TAR0
Load Address in 8 Clocks
Address
1 Clock 1 Clock
Start
CYCTYPE
+
DIR
TAR
1 Clock
Sync
Data
Data Out 2 Clocks
0000b
D[7:4]
D[3:0]
A[31:28] A[27:24]
TAR1