参数资料
型号: SST55LC100M-45-C-BWE
元件分类: 存储控制器/管理单元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA84
封装: 9 X 9 MM, ROHS COMPLIANT, TFBGA-84
文件页数: 4/75页
文件大小: 1040K
代理商: SST55LC100M-45-C-BWE
12
Advance Information
CompactFlash Card Controller
SST55LC100M
2006 Silicon Storage Technology, Inc.
S71316-00-000
3/06
RESET
(Memory Card mode)
1A2
I
I4U
When the pin is high, this signal Resets the CompactFlash
card. The CompactFlash card is Reset only at power up if this
pin is left high or open from power-up. The CompactFlash card
is also Reset when the Soft-Reset bit in the Card Configuration
Option register is set.
RESET
(PC Card I/O mode)
This signal is the same as the PC Card Memory mode signal.
RESET#
(True IDE mode)
In the True IDE mode this input pin is the active low hardware
reset from the host.
WAIT#
(Memory Card mode)
62
F9
O
O1
The WAIT# signal is driven low by the CompactFlash Card to
signal the host to delay completion of a memory or I/O cycle
that is in progress.
WAIT#
(PC Card I/O mode)
This signal is the same as the PC Card Memory mode signal.
IORDY#
(True IDE mode)
In True IDE mode this output signal may be used as IORDY.
WE#
(Memory Card mode)
63
F10
I
I3U
This is a signal driven by the host and used for strobing mem-
ory write data to the registers of the CompactFlash card when
the card is configured in the memory interface mode. It is also
used for writing the configuration registers.
WE#
(PC Card I/O mode)
In PC Card I/O mode, this signal is used for writing the configu-
ration registers.
WE#
(True IDE mode)
In True IDE mode this input signal is not used and should be
connected to VDD by the host.
WP
(Memory Card mode)
55
H8
O
O2
The CompactFlash card does not have a write protect switch.
This signal is held low after the completion of the reset initial-
ization sequence.
IOIS16#
(PC Card I/O mode)
When the CompactFlash card is configured for I/O Operation
Pin 55 is used for the I/O# Selected is 16-bit Port (IOIS16#)
function. A Low signal indicates that a 16 bit or Odd Byte only
operation can be performed at the addressed port.
IOCS16#
(True IDE mode)
In True IDE mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
TABLE
3-1:Pin Assignments (Continued) (4 of 6)
Signal Name
100-lead 84-ball
Pin
Type
I/O
Type1
Name and Functions
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参数描述
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