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ST10F168
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18
POWER REDUCTION MODES ..................................................................................
43
19
SPECIAL FUNCTION REGISTER OVERVIEW............ ..............................................
44
19.1
IDENTIFICATION REGISTERS ..................................................................................
50
20
ELECTRICAL CHARACTERISTICS ......................................................................... .
51
20.1
ABSOLUTE MAXIMUM RATINGS ............. .................................................................
51
20.2
PARAMETER INTERPRETATION..............................................................................
51
20.3
DC CHARACTERISTICS ............................................................................................
51
20.4
A/D CONVERTER CHARACTERISTICS....................................................................
54
20.5
AC CHARACTERISTICS.............................................................................................
55
20.5.1
Test Waveforms ........................................................................................................
55
20.5.2
Definition of Internal Timing.........................................................................................
55
20.5.3
Clock Generation Modes.............................................................................................
56
20.5.4
Prescaler Operation.....................................................................................................
57
20.5.5
Direct Drive.................................................................................................................
.
57
20.5.6
Oscillator Watchdog (OWD) ........................................................................................
57
20.5.7
Phase Locked Loop.....................................................................................................
57
20.5.8
External Clock Drive XTAL1....................... .................................................................
58
20.5.9
Memory Cycle Variables.......................................................................... ....................
59
20.5.10
Multiplexed Bus ............................................................. ..............................................59
20.5.11
Demultiplexed Bus.......................................................................................................
65
20.5.12
CLKOUT and READY.............................................................................. ....................
71
20.5.13
External Bus Arbitration...............................................................................................
73
21
PACKAGE MECHANICAL DATA ................................ ..............................................
75
22
ORDERING INFORMATION .......................................................................................
75