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参数资料
| 型号： | ST10F168-Q2 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 28 X 28 MM, PLASTIC, QFP-144 |
| 文件页数： | 53/76页 |
| 文件大小： | 483K |
| 代理商： | ST10F168-Q2 |
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ST10F168
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20.5.4 - Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during
reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of
fXTAL and the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the
period of the input clock fXTAL.
The timings listed in the AC Characteristics that
refer to TCL therefore can be calculated using the
period of fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
20.5.5 - Direct Drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during
reset the on-chip phase locked loop is disabled and
the CPU clock is directly driven from the internal
oscillator with the input clock signal.
The frequency of fCPU directly follows the
frequency of fXTAL so the high and low time of
fCPU (i.e. the duration of an individual TCL) is
defined by the duty cycle of the input clock fXTAL.
Therefore, the timings given in this chapter refer
to the minimum TCL. This minimum value can be
calculated by the following formula:
For two consecutive TCLs, the deviation caused
by the duty cycle of fXTAL is compensated, so the
duration of 2TCL is always 1/fXTAL. The minimum
value TCLmin has to be used only once for timings
that require an odd number of TCLs (1,3,...).
Timings that require an even number of TCLs
(2,4,...) may use the formula:
Note
The address float timings in Multiplexed
bus mode (t11 and t45) use the maximum
duration of TCL (TCLmax =1/fXTAL x
DCmax) instead of TCLmin.
If bit OWDDIS in the SYSCON register is cleared,
the PLL runs on its free-running frequency and
delivers
the clock
signal for the Oscillator
Watchdog. If bit OWDDIS is set, then the PLL is
switched off.
20.5.6 - Oscillator Watchdog (OWD)
When the clock option selected is direct drive or
direct drive with prescaler, in order to provide a fail
safe mechanism in case of a loss of the external
clock, an oscillator watchdog is implemented as
an additional functionality of the PLL circuitry. This
oscillator watchdog operates as follows :
After a reset, the Oscillator Watchdog is enabled
by default. To disable the OWD, the bit OWDDIS
(bit 4 of SYSCON register) must be set.
When the OWD is enabled, the PLL runs on its
free-running
frequency,
and
increments
the
Oscillator Watchdog counter. On each transition
of XTAL1 pin, the Oscillator Watchdog is cleared.
If an external clock failure occurs, then the
Oscillator Watchdog counter overflows (after 16
PLL clock cycles). The CPU clock signal will be
switched to the PLL free-running clock signal, and
the
Oscillator
Watchdog
Interrupt
Request
(XP3INT) is flagged. The CPU clock will not
switch back to the external clock even if a valid
external clock exits on XTAL1 pin. Only a
hardware reset can switch the CPU clock source
back to direct clock input.
When the OWD is disabled, the CPU clock is
always fed from the oscillator input and the PLL is
switched off to decrease power supply current.
20.5.7 - Phase Locked Loop
For all other combinations of pins P0.15-13
(P0H.7-5) during reset the on-chip phase locked
loop is enabled and provides the CPU clock (see
Table 23).
The PLL multiplies the input frequency by the
factor F which is selected via the combination of
pins P0.15-13 (i.e. fCPU =fXTAL x F). With every
F’th
transition
of
fXTAL
the
PLL
circuit
synchronizes the CPU clock to the input clock.
This synchronization is done smoothly, i.e. the
CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the
frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight variation causes a jitter
of fCPU which also effects the duration of
individual TCL.
The timings listed in the AC Characteristics that
refer to TCL therefore must be calculated using
the minimum TCL that is possible under the
respective circumstances.
TC L
mi n
1f
XTAL
DC
min
×
=
DC
duty cycle
=
2TCL
1 f
XTAL
=
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST10F168Q3 | 制造商:STMicroelectronics 功能描述:MicroController, 16-Bit, 144 Pin, Plastic, QFP |
| ST10F168-Q3 | 制造商:STMicroelectronics 功能描述:MicroController, 16-Bit, 144 Pin, Plastic, QFP |
| ST10F168-Q6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM |
| ST10F168SQ3 | 功能描述:16位微控制器 - MCU 256K Flash 8K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
| ST10F168SQ6 | 功能描述:16位微控制器 - MCU 256K Flash 8K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
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