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参数资料
| 型号： | ST10F168-Q2 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 28 X 28 MM, PLASTIC, QFP-144 |
| 文件页数： | 33/76页 |
| 文件大小： | 483K |
| 代理商： | ST10F168-Q2 |
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ST10F168
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Figure 11 : Synchronous Warm Reset: Long low pulse on RSTIN
Notes 1. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles if the PLL is bypassed and the prescaler is on (fCPU =fXTAL / 2),
else it is 4 CPU clock cycles.
2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the
asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by soft-ware. Bit BDRSTE N is cleared after
reset. If a synchronous reset is used as a power-up reset in place of an asynchronous reset, note that the behaviour of RSTI N (ie.
pulled low or not during 1024 TCL) is undetermined. This should be not a problem, because in such power-up reset, the pin RSTIN
must be maintained to ‘0’ at least during two reset sequences (2*1024 TCL, 40.96
s at 25MHz CPU clock).
17.3 - Software Reset
A software reset sequence can be triggered at
any time by the protected SRST (software reset)
instruction. This instruction can be deliberately
executed within a program, e.g. to leave bootstrap
loader mode, or on a hardware trap that reveals
system failure.
On execution of the SRST instruction, the internal
reset sequence is started. The microcontroller
behaviour is the same as for a synchronous reset,
except that only bit P0.12...P0.8 are latched at the
end of the reset sequence, while previously
latched, bit P0.7...P0.2 are cleared.
17.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during
the initialization, or serviced regularly during pro-
gram execution, it will overflow and trigger the
reset sequence.
Unlike hardware and software resets, the watch-
dog reset completes a running external bus cycle
if this bus cycle either does not use READY, or if
READY is sampled active (low) after the pro-
grammed wait states.
When READY is sampled inactive (high) after the
programmed wait states the running external bus
cycle is aborted. Then the internal reset sequence
is started.
Bit P0.12...P0.8 are latched at the end of the reset
sequence and bit P0.7...P0.2 are cleared.
17.5 - Reset Circuitry
Internal reset circuitry is described in Figure 13.
The RSTIN pin provides an internal pullup resistor
of 50K
to 250K (The minimum reset time must
be calculated using the lowest value).
It also provides a programmable (BDRSTEN bit of
SYSCON register) pulldown to output internal
reset state signal (synchronous reset, watchdog
timer reset or software reset).
This bidirectional reset function is useful in appli-
cations where external devices require a reset
signal but cannot be connected to RSTOUT pin.
This is the case of an external memory running
codes before EINIT ( end of initialization) instruc-
tion is executed. RSTOUT pin is pulled high only
when EINIT is executed.
CPU Clock
RSTIN
VPP
RSTOUT
ALE
Port0
Internal
Reset
Signal
Latching point of Port0
for system start-up configuration
6 or 8 TCL1
4 TCL
12 TCL
1024 TCL
Internally pulled low3
Reset Configuration
2 V
PP > 2.5V AsynchronousReset not entered.
200
A Discharge
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相关代理商/技术参数 |
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| ST10F168Q3 | 制造商:STMicroelectronics 功能描述:MicroController, 16-Bit, 144 Pin, Plastic, QFP |
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| ST10F168SQ3 | 功能描述:16位微控制器 - MCU 256K Flash 8K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
| ST10F168SQ6 | 功能描述:16位微控制器 - MCU 256K Flash 8K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
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