参数资料
型号: ST10F269Z2Q3
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封装: 28 X 28 MM, PLASTIC, QFP-144
文件页数: 102/160页
文件大小: 1541K
代理商: ST10F269Z2Q3
ST10F269
46/160
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable
system
reaction
similar
to
a
standard
interrupt
service
(branching
to
a
dedicated vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prioritized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap services cannot not be interrupted
by standard interrupt or by PEC interrupts.
8.3 - Interrupt Control Registers
All interrupt control registers are
identically
organized. The lower 8 bits of an interrupt control
register contain the complete interrupt status
information of the associated source, which is
required during one round of prioritization, the
upper 8 bits of the respective register are
reserved.
All
interrupt
control
registers
are
bit-addressable and all bits can be read or written
via software.
This
allows
each
interrupt
source
to
be
programmed or modified with just one instruction.
When
accessing
interrupt
control
registers
through instructions which operate on Word data
types, their upper 8 bits (15...8) will return zeros,
when read, and will discard written data.
The layout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
CAPCOM Timer 1
T1IR
T1IE
T1INT
00’0084h
21h
CAPCOM Timer 7
T7IR
T7IE
T7INT
00’00F4h
3Dh
CAPCOM Timer 8
T8IR
T8IE
T8INT
00’00F8h
3Eh
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088h
22h
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008Ch
23h
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090h
24h
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094h
25h
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098h
26h
GPT2 CAPREL Register
CRIR
CRIE
CRINT
00’009Ch
27h
A/D Conversion Complete
ADCIR
ADCIE
ADCINT
00’00A0h
28h
A/D Overrun Error
ADEIR
ADEIE
ADEINT
00’00A4h
29h
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8h
2Ah
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011Ch
47h
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACh
2Bh
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0h
2Ch
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4h
2Dh
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8h
2Eh
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCh
2Fh
PWM Channel 0...3
PWMIR
PWMIE
PWMINT
00’00FCh
3Fh
CAN1 Interface
XP0IR
XP0IE
XP0INT
00’0100h
40h
CAN2 Interface
XP1IR
XP1IE
XP1INT
00’0104h
41h
FLASH Ready / Busy
XP2IR
XP2IE
XP2INT
00’0108h
42h
PLL Unlock/OWD
XP3IR
XP3IE
XP3INT
00’010Ch
43h
Table 7 : Interrupt Sources (continued)
Source of Interrupt or PEC
Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Location
Trap
Number
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