参数资料
型号: ST10F269Z2Q3
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封装: 28 X 28 MM, PLASTIC, QFP-144
文件页数: 12/160页
文件大小: 1541K
代理商: ST10F269Z2Q3
ST10F269
109/160
Figure 56 : Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL)
Note
1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
2) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
3) If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (typically 2.5V for 5V operation), the the
ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.
18.1.3 - Exit of Long Hardware Reset
- If the RPD pin level is low when the RSTIN pin is sampled high, the MCU completes an
asynchronous reset sequence.
-
If the RPD pin level is high when the RSTIN pin is sampled high, the MCU completes a
synchronous reset sequence.
The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU
clocks if PLL is bypassed) and in case of external fetch, ALE, RD and R/W pins are driven to their inactive
level. The MCU starts program execution from
memory location 00'0000h in code segment 0. This
starting location will typically point to the general initialization routine. Refer to Table 29 for PORT0
latched configuration.
18.2 - Short Hardware Reset
A short hardware reset is a warm reset. It may be generated synchronously to the CPU clock
(synchronous reset).
The short hardware is triggered when RSTIN signal duration is shorter or equal to 1038 TCL, the
RPD pin must be pulled high.
To properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at least, during
4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is driven low.
After RSTIN level is detected, a short duration of 12 TCL (6 CPU clocks) maximum elapses, during which
pending internal hold states are cancelled and the current internal access cycle if any is completed.
External bus cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of
SYSCON register was previously set by software. This bit is always cleared on power-on or after any
reset sequence.
The internal reset sequence starts for 1024 TCL (512 periods of CPU clock).
After that duration the pull-down of RSTIN pin for the bidirectional reset function is released and the
RSTIN pin level is sampled high while RPD level is high.
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0
Latching point of PORT0
for system start-up configuration
6 or 8 TCL1)
4 TCL
12 TCL
min.
max.
1024 TCL
Reset Configuration
If VRPD > 2.5V Asynchronous
200
A Discharge
3)
RD
4
3
2
1
5
67
8
9
Reset is not entered.
Internal reset signal
Internally pulled low
2)
5 TCL
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