参数资料
型号: ST10F269Z2Q3
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封装: 28 X 28 MM, PLASTIC, QFP-144
文件页数: 75/160页
文件大小: 1541K
代理商: ST10F269Z2Q3
ST10F269
21/160
5.3.5 - Flash Protection Register
The Flash Protection register is a non-volatile register that contains the protection status. This register
can be read by using the Read Protection Status (RP) command, and programmed by using the dedi-
cated Set Protection command.
Flash Protection Register (PR)
5.3.6 - Instructions Description
Twelve instructions dedicated to Flash memory
accesses are defined as follow:
Read/Reset (RD). The Read/Reset instruction
consist of one write cycle with data XXF0h . it can
be optionally preceded by two CI enable coded
cycles (data xxA8h at address 1554h + data
xx54h at address 2AA8h). Any successive read
cycle following a Read/Reset instruction will read
the memory array. A Wait cycle of 10s is
necessary after a Read/Reset command if the
memory was in program or Erase mode.
Program Word (PW). This instruction uses four
write cycles. After the two Cl enable coded cycles,
the Program Word command xxA0h is written at
address 1554h. The following write cycle will latch
the address and data of the word to
be
programmed. Memory programming can be done
only by writing 0's instead of 1's, otherwise an
error occurs. During programming, the Flash
Status is checked by reading the Flash Status bit
FSB.2, FSB.5, FSB.6 and FSB.7 which show the
status of the EPC. FSB.2, FSB.6 and FSB.7
determine if programming is on going or has
completed, and FSB.5 allows a check to be made
for any possible error.
Block Erase (BE). This instruction uses a
minimum of six command cycles. The erase
enable command xx80h is written at address
1554h after the two-cycle CI enable sequence.
The erase confirm code xx30h must be written at
an address related to the block to be erased
preceded by the execution of a second CI enable
sequence. Additional erase confirm codes must
be given to erase more than one block in parallel.
Additional erase confirm commands must be
written within a defined time-out period. The input
of a new Block Erase command will restart the
time-out period.
When this time-out period has elapsed, the erase
starts. The status of the internal timer can be
monitored through the level of FSB.3, if FSB.3 is
‘0’, the Block Erase command has been given and
the timeout is running; if FSB.3 is ‘1’, the timeout
has expired and the EPC is erasing the block(s).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CP
-
BP6
BP5
BP4
BP3
BP2
BP1
BP0
BPx
Block x Protection Bit (x = 0...6)
‘0’: the Block Protection is enabled for block x. Programming or erasing the block is not
possible, unless a Block Temporary Unprotection command is issued.
1’: the Block Protection is disabled for block x.
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Block Protection using the Block Temporary Unprotection instruction.
CP
Code Protection Bit
‘0’: the Flash Code Protection is enabled. Read accesses to the Flash for execution not
performed in the Flash itself are not allowed, the returned value will be 009Bh, whatever the
content of the Flash is.
1’: the Flash Code Protection is disabled: read accesses to the Flash from external or internal
RAM are allowed
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Code Protection using the Code Temporary Unprotection instruction.
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