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参数资料
型号： ST52E430B/D
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 40/120页
文件大小： 502K
代理商： ST52E430B/D
26/120
ST52T430/E430
the EPROM operations, changing the Memory
Lock Status from 0 to 1 .
RST_ADD signal resets the memory address
register and the Memory Lock Status. For this
reason, when the RST_ADD becomes high, it is
necessary to unlock the memory to read or write.
INC_ADD signal increments the memory
address.
RST_CONF signal resets the EPROM
Configuration Register. When RST_CONF is
high, the DATA I/O Port A is in output, otherwise
it is always in input.
INC_CONF signal increments the EPROM
Configuration Register value.
PHASE signal validates the operation selected by
means of EPROM Configuration Register value.
3.1.1 EPROM Operation
To execute one EPROM operation (See Table 3.1),
the corresponding identification value must be
loaded in the EPROM Configuration Register. The
signal timing is the following: RST_ADD= high and
PHASE= high, RST_CONF changes from low to
high level, to reset the EPROM Configuration
Register, and INC_CONF signal generates a
number of positive pulses equal to the value to be
loaded. After this sequence, a negative pulse of
the PHASE signal will validate the selected
operation. The minimum PHASE signal pulse
width must be 10 ms for the EPROM Writing
Operation and 100 ns for the others.
When RST_CONF is high, the DATA I/O Port A is
enabled in output and the reading / verify
operation results are available.
After a writing operation, when RST_CONF is high,
the Port A is in output with no valid data.
3.1.2 EPROM Locking
The Memory Lock operation, that is identified with
the number 4 in the EPROM Configuration
Register, writes “0" in the Memory Lock Cell.
At the beginning of an External Operation, when
RST_ADD signal changes from low level to high
level, the Memory Lock Status is “0", therefore it is
necessary to unlock it before to proceed.
To unlock the Memory Lock Status the operation,
that is identified with the number 2 in the EPROM
Configuration Register must be executed (see
Figure 3.2).
The Memory Lock Status can be changed only if
Memory Lock Cell is “1", therefore, for this reason,
after a Memory Lock operation it is not possible to
execute external operations except to read (or
verify) the OTP Code and the Memory Lock Status
3.1.3 EPROM Writing
When the memory is blank, all the bits are at logic
level “1". The data are introduced by programming
only the zeros in the desired memory location;
however all input data must contain both ”1" and
“0".
The only way to change “0" into ”1" is to erase the
whole memory (by exposure to Ultra Violet light)
and reprogram it.
The memory is in Writing mode when the EPROM
Configuration Register value is 3.
The VPP voltage must be 12V±5%, with stable data
on the data bus PA(0:7).
The signals timing is the following (see Figure 3.2):
1) RST_ADD and RST_CONF change from low to
high level,
2) two pulses on INC_CONF signal load the
Memory Unlock operation code,
3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Unlock operation,
4) a negative pulse on RST_CONF signal resets
the EPROM Configuration Register,
5) three positive pulses on INC_CONF load the
Memory Writing operation code,
6) a train of positive pulses on INC_ADD signal
increments the memory location address up to the
requested value (generally this is a sequencial
operation and only one pulse is used),
7) a negative pulse (10 ms) on the PHASE signal
validates the Memory Writing operation,
3.1.4 EPROM Reading / Verify Margin Mode
The reading phase is executed with VPP=5V±5%,
instead of verify phase that needs VPP= 12V±5%.
The Memory Verify operation is available in order
to verify the correctness of the data written. It is
possible to execute a Memory Verify Margin Mode
operation immediately after the writing of each
byte and in this case (see Figure 3.2):
1) a positive pulse on RST_CONF signal resets the
EPROM Configuration Register, if it was not
already reseted
2) one positive pulse on INC_CONF load the
Memory Reading/Verify operation code,
3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Reading / Verify operation,
4) a negative pulse on RST_CONF signal puts in
the PA(0:7) port the value stored in the actual
memory address and resets the EPROM
Configuration Register.
Then, if any error in writing occurred, the user has
to repeat the EPROM writing.
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