参数资料
型号: ST52E430B/D
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封装: WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数: 62/120页
文件大小: 502K
代理商: ST52E430B/D
46/120
ST52T430/E430
8 WATCHDOG TIMER
8.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a
programmed time period, unless the program
refreshes the WDT before the end of the
programmed time delay.
16 different delay can be selected by using the
WDT configuration register.
If the WDT is activated (by using the assembler
instruction WDTSFR) after the end of the delay
programmed by the configuration register, it start a
reset cycle pulling low the reset pin.
The application program once activated the WDT
has to refresh this peripheral (by the WDTSFR
instruction) at regular intervals during normal
operation to prevent an MCU reset.
To stop the WDT during the user program
executions the instruction WDTSLP has to be used.
The working frequency of the WDT (PRES CLK in
the Figure 8.1) is equal to the clock master. The
clock master is then divided by 500 thus obtaining
the WDT CLK signal that is used to fix the timeout of
the WDT.
D0
D1
D2
D3
REG_CONF 2
RESET
WDTRFR
PRES CLK = CLK MASTER
WDTSLP
PRESCALER
WDT
RESET
GENERATOR
RESET
WTD CLK
Figure 8.1 Watchdog Block Diagram
According to the WDT configuration register
values it possible to define a WDT delay between
0.1 mS and 937.5 mS when the clock master is 5
MHz. Changing the clock master frequency the
timeout delay can be calculated according to the
configuration register values REG_CONF 2 as
described in the following section.
WDT timeout period (mS)
min
0.1
max
937.5
Table 8.1 Watchdog Timing range (CLK=5
MHz)
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