参数资料
型号: ST52E430B/D
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封装: WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数: 65/120页
文件大小: 502K
代理商: ST52E430B/D
49/120
ST52T430/E430
externally by setting T0RST, T0STR, T0CLK bits of
REG_CONF7 register.
TMRCLKx is the Prescaler x output, that
increments, on the rising edge, the Counter x
value. TMRCLKx is obtained from the internal
clock signal (CLKM) or, only for TIMER0, from the
external signal provided on the PA5/T0CLK pin.
NOTE: The external clock signal, applied on
T0CLK pin, must have a frequency at least two
times smaller than the internal master clock.
The prescaler output can be selected by setting
PRESCx bit of REG_CONF6, REG_CONF9 and
REG_CONF11 registers (see tables 9.2, 9.5 and
9.7).
TxRES resets to zero the content of the 8-bit
counter x. It is generated by the TIRSTx and
TxMSK bits of REG_CONF5, REG_CONF7,
REG_CONF8 and REG_CONF10 registers (see
tables 9.1, 9.3, 9.4 and 9.6).
TxSTRT signal start/stop the Timer x counting. This
signal is forced by setting the correspondent
TISTRx bit of REG_CONF5, REG_CONF8 and
REG_CONF10 registers (see tables 9.1, 9.4 and
9.6).
TxMSK bits mask the reset of each timer and, for
this reason, they can be utilized to synchronize a
simultaneous start of the timers, by means, for
example, of the following procedure that starts
three timers:
1) TIRST0 = TIRST1 = TIRST2 = 0,
2) TISTR0 = TISTR1 = TISTR2 = 0,
3) T0MSK = T1MSK = T2MSK = 1,
4) TIRST0 = TIRST1 = TIRST2 = 1,
5) TISTR0 = TISTR1 = TISTR2 = 1,
6) T0MSK = T1MSK = T2MSK = 0,
(all timers start simultaneously)
When TxMSK is 1 the TIMER x is reseted.
TIMER 0 START/STOP can be given externally on
the T0STRT pin. In this case, T0STRT signal allows
to work in two different modes, by setting the
TESTR configuration bit of REG_CONF5 register
(see figure 9.2) (Input capture):
LEVEL (Time Counter): If the T0STRT signal is
high the Timer starts the count. When the T0STRT
is low the counting is stopped and the current
value is stored in the PWM_0_COUNT Input
Register.
Timer Outpu
Type 1
Type 2
Prescout*Counter
Figure 9.3. TIMEROUT Signal Type
Level
Edge
start
stop
start
stop
start
01
1
0
4
3
2
Reset
Clock
Counted
Value
Figure 9.2. Timer 0 External START / STOP Mode
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