参数资料
型号: ST52E430B/D
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封装: WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数: 44/120页
文件大小: 502K
代理商: ST52E430B/D
3/120
ST52T430/E430
START/STOP signals and clock. It includes Input
Capture (IC) and Output Compare (OC) functions.
An internal programmable watchdog is available
to avoid loop error and reset the micro controller.
In order to reduce the energy consumption,
ST52x430 is able to perform two different power
saving features : Wait mode and Halt mode.
The EPROM contains the micro controller
configuration, in terms of I/O number, microcode,
Fuzzy Rules and Membership Functions (MFs).
ST52x430 processes inputs and produces the
related outputs according to the configuration
loaded during the programming phase (stored
into the EPROM).
ST52x430 includes an 8-bit Analog to Digital
Converter with a 8-analog channel
Multiplexer.
A Serial Communication peripheral (SCI) using
the UART protocol allows to transfer data from the
ST52x430 to others external devices.
A powerful development environment consisting
of board and software allows an easy
configuration and use of ST52x430.
Operations on the data stored in the RAM (256
bytes), allowing to directly combine new inputs
and feedback data can be easily performed by
using a Registers File approach. All the 256 bytes
of RAM are used like Registers File.
It is possible to perform 16 bit over 8 bit
arithmetical divisions, with 8 bit result and 8 bit
remainder and 8 bit by 8 bit arithmetical
multiplications, with 16 bit result.
ST52x430 is fully supported by FUZZYSTUDIO 4.0
allowing to graphically design a project and obtain
an optimized microcode.
ST52x430 exploits a STMicroelectronics patented
strategy to store the MFs in its internal memory.
FUNCTIONAL DESCRIPTION
ST52x430 works in two modes according to the
control signal level.
ST52x430 is a programmable product and its
operation phases are:
n
Memory Programming Phase
n
Working Phase
These phases are selected by using the following
signals (see pins description):
RESET
TEST
Vpp
Memory Programming Phase
ST52x430 memory is loaded in Memory
Programming Phase. All fuzzy and standard
instructions are written inside the memory.
This phase starts with the setting of the control
signals as follows:
RESET
TEST
VPP
Vss
12V/VDD
When this phase starts, ST52x430 core is set to the
RESET status. This allows to program and/or to
test the internal Eprom. (see Eprom
programming).
Working Mode
In this mode the control signals are the following :
RESET
TEST
VPP
VDD
VSS
The processor starts the working phase following
the instructions which have been previously
loaded in the memory.
Figure 2.4 shows the internal structure of
ST52x430. It is composed by one computational
block: the CONTROL UNIT (CU) / DPU block,
which allows the implementation of the fuzzy
calculus and the performing of boolean functions.
The CU/DPU is able to manage up to 341 different
Membership Functions for the antecedent part of
the fuzzy rules. The rules consequents are “crisp”
values (real numbers). The number of possible
rules is related with the dimensions of the
implemented standard algorithm. Smaller
standard algorithms allow to define bigger fuzzy
algorithms with more rules and viceversa. The 8
kbytes of the Eprom are then shared between
fuzzy and standard algorithms.
The Control Unit (CU) read the information and the
status incoming from the peripherals.
The arithmetic calculus can be performed on these
values by using the internal CU and the 256 bytes
RAM, which supports all computations.
The inputs of the peripherals can be the fuzzy
and/or arithmetic outputs, or the values contained
in Data RAM and EPROM locations.
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