参数资料
型号: ST72324K6B3/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封装: 0.400 INCH, SHRINK, PLASTIC, DIP-32
文件页数: 70/157页
文件大小: 1037K
代理商: ST72324K6B3/XXX
Table of Contents
157
2/157
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . ... .. .. ... .. . ... .. . . ... .. . 7
2 PIN DESCRIPTION . . . . . . . . . . . . .... . ... .. . . .. .... .... .. . . . . . . . . . . . . . ... .. . .... . 8
3 REGISTER & MEMORY MAP . . . .... .. . . . . . . . . .... . ... .. .. .. . .... ... . . . . . . . . . . . . 13
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... .. . . .. . 17
4.1
INTRODUCTION . .... .. . .... . ... .. .. ... ... . . . . . . . . ... .. . . ... . ... . . . . ... 17
4.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .... .. . . . . . . . . . . 17
4.3
STRUCTURE . . . .... ... . . . . . . . . ... .. . . ... . . . .... . . . .... .... .. . .... .. . . . 17
4.3.1
Read-out Protection . . . . . . . . . . . . . . . . . . . . . .... . . . .... .... .. . . . . . . . . . . 17
4.3.2
Flash Write/Erase Protection . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . . 17
4.4
ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . . 18
4.5
ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... 19
4.6
IAP (IN-APPLICATION PROGRAMMING) . .... . ... .. .. .. .... . . . ... . . . . . . . . . . 19
4.6.1
Register Description . . . . . .... . . ... .. .... ... . . . . . . . . . . . . . . . . . .. . ... .. 19
5 CENTRAL PROCESSING UNIT . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . . . . . 20
5.1
INTRODUCTION . .... .. . .... . ... .. .. ... ... . . . . . . . . ... .. . . ... . ... . . . . ... 20
5.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .... .. . . . . . . . . . . 20
5.3
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . . 20
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. 23
6.1
PHASE LOCKED LOOP . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . . 23
6.2
MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. 24
6.3
RESET SEQUENCE MANAGER (RSM) . . . . . .... ... . . . . . . . . . . . . . . . . . .. . ... .. 25
6.3.1
Introduction . . . . . . . . . . . . .... . . ... .. .... ... . . . . . . . . . . . . . . . . . . . . ... .. 25
6.3.2
Asynchronous External RESET pin . . . .... .... .. . . . . . . . . . . . . . ... .. . .... 25
6.3.3
External Power-On RESET . . . . . . . . . . . . . . . .... . . . .... . ... .. . . ... .. . . . 26
6.3.4
Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . .... . . ... .. 26
6.3.5
Internal Watchdog RESET . . . . . . ... . . . . . . . . . ... .. .. ... .. .. .... . . ... .. 26
6.4
SYSTEM INTEGRITY MANAGEMENT (SI) .... . ... .. .. .. .... . . . ... . . . . . . . . . . 27
6.4.1
Low Voltage Detector (LVD) . . . . . . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... 27
6.4.2
Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. 28
6.4.3
Clock Security System (CSS) . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . . 29
6.4.4
Low Power Modes . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . . 29
6.4.5
Register Description . . . . . .... . . ... .. .... ... . . . . . . . . . . . . . . . . . .. . ... .. 30
7 INTERRUPTS . . .... .. . . . . . . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . . . . . 31
7.1
INTRODUCTION . .... .. . .... . ... .. .. ... ... . . . . . . . . ... .. . . ... . ... . . . . ... 31
7.2
MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3
INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4
CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . 33
7.5
INTERRUPT REGISTER DESCRIPTION . . . .... .... .. . . . . . . . . . . . . . ... .. . .... 34
7.6
EXTERNAL INTERRUPTS . . . . . . . . . . . . . .... . ... .. . . . . .... . . . . .. . . . . . . . . . . 35
7.6.1
I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . .... .... .. . . . . . . . . . . 35
7.7
EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . .... .... .. . . . . . . . . . . 37
8 POWER SAVING MODES . . . . . . . . . . .... . . ... .. .... ... . . . . . . . . . . . . . . . . . .. . ... .. 39
8.1
INTRODUCTION . .... .. . .... . ... .. .. ... ... . . . . . . . . ... .. . . ... . ... . . . . ... 39
8.2
SLOW MODE . . . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. 39
2
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