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参数资料
| 型号： | ST72324K6B3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 0.400 INCH, SHRINK, PLASTIC, DIP-32 |
| 文件页数： | 86/157页 |
| 文件大小： | 1037K |
| 代理商： | ST72324K6B3/XXX |
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ST72324J/K
34/157
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read/Write
Reset Value: 111x 1010 (xAh)
Bit 5, 3 = I1, I0
Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TLI, TRAP and RESET events are non
maskable sources and can interrupt a level 3 pro-
gram.
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
70
11
I1
H
I0
NZ
C
Interrupt Software Priority
Level
I1
I0
Level 0 (main)
Low
High
10
Level 1
0
1
Level 2
0
Level 3 (= interrupt disable*)
1
70
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11 I0_11 I1_10 I0_10 I1_9
I0_9
I1_8
I0_8
ISPR3
1
I1_13 I0_13 I1_12 I0_12
Vector address
ISPRx bits
FFFB h-FFFAh
I1_0 and I0_0 bits*
FFF9h-FF F8h
I1_1 and I0_1 bits
...
FFE1h-FFE0h
I1_13 and I0_13 bits
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72324K6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE |
| ST72324Kx | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,10-BIT ADC, 4 TIMERS,SPI,SCI INTERFACE |
| ST72324LJ2 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324LJ4 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324LJ6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
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