参数资料
型号: ST72E331N4D0
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56
封装: 0.600 INCH, WINDOWED, CERAMIC, SDIP-56
文件页数: 25/107页
文件大小: 691K
代理商: ST72E331N4D0
24/107
ST72E331 ST72T331
4.4 POWER SAVING MODES
4.4.1 Introduction
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis-
cellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
4.4.2 Slow Mode
In Slow mode, the oscillator frequency can be di-
vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
4.4.3 Wait Mode
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU will remain in Wait mode until an Inter-
rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In-
terrupt or Reset Service Routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Refer to Figure 18 below.
Figure 18. WAIT Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
CLEARED
OFF
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
4096 CPU CLOCK
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
24
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