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参数资料
| 型号： | ST72E331N4D0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56 |
| 封装： | 0.600 INCH, WINDOWED, CERAMIC, SDIP-56 |
| 文件页数： | 80/107页 |
| 文件大小： | 691K |
| 代理商： | ST72E331N4D0 |
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ST72E331 ST72T331
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.6.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 4, shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin, the
MOSI pin are directly connected between the mas-
ter and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 3).
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 3).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 42. CPHA / SS Timing Diagram
MOSI/ MISO
Master
SS
Slave
SS
(CPHA=0)
Slave
SS
(CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131A
74
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| ST72T331J4T6S | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72E331N4D0S | 功能描述:8位微控制器 -MCU UV EPROM 16K RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72E4K64-A75EC | 制造商:STEC Inc 功能描述:512MB DDR-266 ECC/REG - Bulk |
| ST72E4K64ML-C06E | 制造商:STEC Inc 功能描述:512MB 512MB DDR PC2700 REG/ECC |
| ST72E4L128ML-C06E | 制造商:STEC Inc 功能描述:SimpleTech 1GB PC2700 333MHz ECC Registered DDR DIMM Memory |
| ST72E63-EPB/US | 功能描述:程序设计器 - 基于处理器 ST7 EPROM Programmer RoHS:否 制造商:Olimex Ltd. 产品:Programmers 工具用于评估:XMEGA, MegaAVR, tinyAVR 核心:AVR 接口类型:USB 工作电源电压:1.8 V to 5.5 V |
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