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参数资料
| 型号： | ST72E331N4D0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56 |
| 封装： | 0.600 INCH, WINDOWED, CERAMIC, SDIP-56 |
| 文件页数： | 88/107页 |
| 文件大小： | 691K |
| 代理商： | ST72E331N4D0 |
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ST72E331 ST72T331
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF
Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL
Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 5).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF
Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 0.1.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 2 ).
70
SPIF
WCOL
-
MODF
-
70
D7
D6
D5
D4
D3
D2
D1
D0
81
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72E331N4D0S | 功能描述:8位微控制器 -MCU UV EPROM 16K RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72E4K64-A75EC | 制造商:STEC Inc 功能描述:512MB DDR-266 ECC/REG - Bulk |
| ST72E4K64ML-C06E | 制造商:STEC Inc 功能描述:512MB 512MB DDR PC2700 REG/ECC |
| ST72E4L128ML-C06E | 制造商:STEC Inc 功能描述:SimpleTech 1GB PC2700 333MHz ECC Registered DDR DIMM Memory |
| ST72E63-EPB/US | 功能描述:程序设计器 - 基于处理器 ST7 EPROM Programmer RoHS:否 制造商:Olimex Ltd. 产品:Programmers 工具用于评估:XMEGA, MegaAVR, tinyAVR 核心:AVR 接口类型:USB 工作电源电压:1.8 V to 5.5 V |
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