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| 型号： | ST72E331N4D0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56 |
| 封装： | 0.600 INCH, WINDOWED, CERAMIC, SDIP-56 |
| 文件页数： | 47/107页 |
| 文件大小： | 691K |
| 代理商： | ST72E331N4D0 |
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ST72E331 ST72T331
16-BIT TIMER (Cont’d)
5.4.3.3 Input Capture
In this section, the index,
i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected by the
ICAP
i pin (see figure 5).
The IC
iR register is a read-only register.
The active transition is software programmable
through the IEDG
i bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (
fCPU/CC[1:0]).
Procedure:
To use the input capture function, select the fol-
lowing in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 1).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as a floating input).
When an input capture occurs:
– The ICF
i bit is set.
– The IC
iR register contains the value of the free
running counter on the active transition on the
ICAP
i pin (see Figure 6).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICF
i bit) is done in two steps:
1. Reading the SR register while the ICF
i bit is set.
2. An access (read or write) to the IC
iLR register.
Notes:
1. After reading the IC
iHR register, the transfer of
input capture data is inhibited and ICF
i will
never be set until the IC
iLR register is also
read.
2. The IC
iR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One Pulse mode and PWM mode only the
input capture 2 function can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
Moreover if one of the ICAP
i pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion
i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with an interrupt in
order to measure events that exceed the timer
range (FFFFh).
MS Byte
LS Byte
ICiR
IC
iHR
IC
iLR
44
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72E331N4D0S | 功能描述:8位微控制器 -MCU UV EPROM 16K RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72E4K64-A75EC | 制造商:STEC Inc 功能描述:512MB DDR-266 ECC/REG - Bulk |
| ST72E4K64ML-C06E | 制造商:STEC Inc 功能描述:512MB 512MB DDR PC2700 REG/ECC |
| ST72E4L128ML-C06E | 制造商:STEC Inc 功能描述:SimpleTech 1GB PC2700 333MHz ECC Registered DDR DIMM Memory |
| ST72E63-EPB/US | 功能描述:程序设计器 - 基于处理器 ST7 EPROM Programmer RoHS:否 制造商:Olimex Ltd. 产品:Programmers 工具用于评估:XMEGA, MegaAVR, tinyAVR 核心:AVR 接口类型:USB 工作电源电压:1.8 V to 5.5 V |
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