参数资料
型号: ST72E331N4D0
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56
封装: 0.600 INCH, WINDOWED, CERAMIC, SDIP-56
文件页数: 56/107页
文件大小: 691K
代理商: ST72E331N4D0
52/107
ST72E331 ST72T331
16-BIT TIMER (Cont’d)
5.4.4 Low Power Modes
5.4.5 Interrupts
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
5.4.6 Summary of Timer modes
1) See note 4 in Section 0.1.3.5 One Pulse Mode
2) See note 5 in Section 0.1.3.5 One Pulse Mode
3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode
Mode
Description
WAIT
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAP
i pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF
i bit is set, and
the counter value present when exiting from HALT mode is captured into the IC
iR register.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Input Capture 1 event/Counter reset in PWM mode
ICF1
ICIE
Yes
No
Input Capture 2 event
ICF2
Yes
No
Output Compare 1 event (not available in PWM mode)
OCF1
OCIE
Yes
No
Output Compare 2 event (not available in PWM mode)
OCF2
Yes
No
Timer Overflow event
TOF
TOIE
Yes
No
MODES
AVAILABLE RESOURCES
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Yes
Output Compare (1 and/or 2)
Yes
One Pulse mode
No
Not Recommended1)
No
Partially 2)
PWM Mode
No
Not Recommended3)
No
52
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