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参数资料
| 型号： | ST72E331N4D0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56 |
| 封装： | 0.600 INCH, WINDOWED, CERAMIC, SDIP-56 |
| 文件页数： | 36/107页 |
| 文件大小： | 691K |
| 代理商： | ST72E331N4D0 |
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ST72E331 ST72T331
EEPROM (Cont’d)
5.2.3 Functional description
5.2.3.1 Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the CR register is
cleared. In a read cycle, the desired byte is put on
the data bus in less than 1 CPU clock cycle. This
means that reading data from EEPROM takes the
same time as reading data from EPROM, but this
memory cannot be used to execute machine code.
5.2.3.2 Write operation (E2LAT=1)
The EEPROM programming flowchart is shown in
Figure 24.
To access write mode set the E2LAT bit, the
E2PGM bit stays cleared. Then when a write ac-
cess to the EEPROM occurs, the value on the data
bus is latched on the 16 data latches depending
on the address.
When E2PGM is set, all the previous bytes written
(1 up to 16) are programmed in the EEPROM
cells. The effective high address (row) is deter-
mined by the last EEPROM write sequence. To
avoid wrong programming, the user must take
care that all the bytes written between two pro-
gramming sequences have the same high ad-
dress: only the four Least Significant Bits of the ad-
dress can change.
At the end of the cycle, the E2PGM and E2LAT
bits are cleared simultaneously, and an interrupt is
generated if the E2ITE bit is set.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of
E2LAT bit.
It is not possible to read the latched data.
5.2.3.3 EEPROM Access Error handling
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
34
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72E331N4D0S | 功能描述:8位微控制器 -MCU UV EPROM 16K RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72E4K64-A75EC | 制造商:STEC Inc 功能描述:512MB DDR-266 ECC/REG - Bulk |
| ST72E4K64ML-C06E | 制造商:STEC Inc 功能描述:512MB 512MB DDR PC2700 REG/ECC |
| ST72E4L128ML-C06E | 制造商:STEC Inc 功能描述:SimpleTech 1GB PC2700 333MHz ECC Registered DDR DIMM Memory |
| ST72E63-EPB/US | 功能描述:程序设计器 - 基于处理器 ST7 EPROM Programmer RoHS:否 制造商:Olimex Ltd. 产品:Programmers 工具用于评估:XMEGA, MegaAVR, tinyAVR 核心:AVR 接口类型:USB 工作电源电压:1.8 V to 5.5 V |
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