参数资料
型号: ST72E331N4D0
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP56
封装: 0.600 INCH, WINDOWED, CERAMIC, SDIP-56
文件页数: 39/107页
文件大小: 691K
代理商: ST72E331N4D0
37/107
ST72E331 ST72T331
5.3 WATCHDOG TIMER (WDG)
5.3.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
5.3.2 Main Features
s
Programmable timer (64 increments of 12288
CPU cycles)
s
Programmable reset
s
Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
s
Hardware Watchdog selectable by option byte
s
Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
5.3.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
Figure 25. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
fCPU
T6
T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷12288
T1
T2
T3
T4
T5
37
相关PDF资料
PDF描述
ST72T331N2B6S 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP56
ST72T331J2T3S 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP44
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ST72T331N2T6S 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64
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