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参数资料
| 型号： | ST7PL35F2MCXXXRE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20 |
| 文件页数： | 105/168页 |
| 文件大小： | 2955K |
| 代理商： | ST7PL35F2MCXXXRE |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
41/168
POWER SAVING MODES (cont’d)
9.4.0.1 Halt Mode Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” or “floating inter-
rupt” before executing the HALT instruction. The
main reason for this is that the I/O may be wrong-
ly configured due to external interference or by
an unforeseen logical condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in pro-
gram memory with the value 0x8E.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
9.5 ACTIVE HALT MODE
ACTIVE HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
(RTC) available. It is entered by executing the
‘HALT’ instruction. The decision to enter either in
ACTIVE HALT or HALT mode is given by the LTC-
SR/ATCSR register status as shown in the follow-
ing table:.
The MCU can exit ACTIVE HALT mode on recep-
tion of a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 36) or a RESET.
– When exiting ACTIVE HALT mode by means of
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
– When exiting ACTIVE HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 27).
When entering ACTIVE HALT mode, the I bit in the
CC register is cleared to enable interrupts. There-
fore, if an interrupt is pending, the MCU wakes up
immediately (see Note 3).
In ACTIVE HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Note: As soon as ACTIVE HALT is enabled, exe-
cuting a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
LTCSR1
TB1IE bit
ATCSR
OVFIE1
bit
ATCSR
CK1 bit
ATCSR
CK0 bit
Meaning
0x
x
0
ACTIVE HALT
mode disabled
00
x
1x
x
ACTIVE HALT
mode enabled
x1
0
1
相关PDF资料 |
PDF描述 |
|---|---|
| ST7PL35F2UA/XXXE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7L35F2UA/XXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7L35F2UC/XXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7L39F2MC/XXXE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| ST7L39F2UC/XXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
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