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参数资料
型号： ST7PLITEUS5M6TR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
封装： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件页数： 30/108页
文件大小： 1957K
代理商： ST7PLITEUS5M6TR
ST7LITEUSx
28/108
7.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to “Illegal Opcode Reset” on page 64 for further
details.
7.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the VDD supply voltage is
below a VIT-(LVD) reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is
lower than the VIT+(LVD) reference value for power-
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–VIT+(LVD) when VDD is rising
–VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option
byte to be low, medium or high. See section 14.1
on page 95.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-(LVD), the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the ap-
plication, it is recommended to pull VDD down to
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 63 on page 87 and note
4.
The LVD is an optional function which can be se-
lected by option byte. See section 14.1 on page
95. It allows the device to be used without any ex-
ternal RESET circuitry. If the LVD is disabled, an
external circuitry must be used to ensure a proper
power-on reset.
It is recommended to make sure that the VDD sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Make sure the right combination of LVD and AVD
thresholds is used as LVD and AVD levels are not
correlated. Refer to section 12.3.2 on page 70 and
section 12.3.3 on page 70 for more details.
Caution: If an LVD reset occurs after a watchdog
reset has occurred, the LVD will take priority and
will clear the watchdog flag.
Figure 15. Low Voltage Detector vs Reset
VDD
VIT+(LVD)
RESET
VIT-(LVD)
Vhys
1
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