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| 型号： | ST7PLITEUS5M6TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, LEAD FREE, PLASTIC, SOP-8 |
| 文件页数： | 90/108页 |
| 文件大小： | 1957K |
| 代理商： | ST7PLITEUS5M6TR |
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I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 48. Typical IPU vs. VDD with VIN=VSS
l
12.8.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.
3. Not tested in production, based on characterization results.
Symbol
Parameter
Conditions
Min
Max
Unit
VOL
1)
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 51)
V
DD
=5V
IIO=+5mA,TA≤125°C
1200
mV
IIO=+2mA,TA≤125°C
400
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 54)
IIO=+20mA,
TA≤125°C
1300
IIO=+8mA,TA≤125°C
750
VOH
2)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 58)
IIO=-5mA,TA≤125°C
VDD-1500
IIO=-2mA,TA≤125°C
VDD-800
VOL
1)3)
Output low level voltage for PA3/RESET standard
I/O pin
(see Figure 50)
V
DD
=3V
IIO=+2mA,TA≤125°C
250
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 53)
IIO=+2mA,TA≤125°C
150
IIO=+8mA,TA≤125°C
500
VOH
2)3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 56)
IIO=-2mA,TA≤125°C
VDD-800
VOL
1)3)
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 49)
V
DD
=2.4V
IIO=+2mA,TA≤125°C
500
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 52)
IIO=+2mA,TA≤125°C
200
IIO=+8mA,TA≤125°C
600
VOH
2)3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 55)
IIO=-2mA,TA≤125°C
VDD-900
0
10
20
30
40
50
60
70
80
90
2.
4
2.
8
3.
2
3.
6
4
4.
4
4.
8
5.
2
5.
6
VDD [V]
IP
U
[u
A
]
-45°C
25°C
90°C
1
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