参数资料
型号: ST7PLITEUS5M6TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
封装: 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件页数: 7/108页
文件大小: 1957K
代理商: ST7PLITEUS5M6TR
ST7LITEUSx
104/108
15 KNOWN LIMITATIONS
15.1 LIMITATIONS IN USER MODE
15.1.1 Flash Memory Access when Exiting
from HALT Mode
Description
When exiting from HALT mode, the CPU starts to
run after 64 cycles.
However, to work properly and to be accessed
safely, the Flash memory needs a delay of 42 s.
This problem occurs only with a CPU frequency
from 2MHz to 8MHz (i.e. with a wake-up time from
Halt mode respectively from 32s to 8s).
This limitation is NOT present in the following
cases:
– at power-on (as an additional delay of 34s is al-
ways applied)
– for internal reset as Flash memory cells are not
stopped.
Workaround
The CPU frequency must be set by software at
1MHz before entering HALT mode.
When the CPU exits from HALT mode by an exter-
nal reset, the reset pulse of at least 42s must be
applied.
15.1.2 Spurious AVD Interrupt when AVD
Switches ON and LVD is OFF
Description
If LVD is selected OFF by the option bytes, when
the AVD is turned ON by selecting one of the three
levels with the AVDTHCR register, a spurious
AVD interrupt is generated.
Workaround
In the application using an AVD threshold with
LVD OFF, the user can insure that the AVD inter-
rupt is not a spurious one by checking if AVDF is
ON when entering the AVD interrupt subroutine.
15.2 LIMITATIONS IN ICC MODE
These limitations can concern ICP (programming)
and/or ICD (debugging) and a workaround (when
available) should be implemented in any program-
ming or debugging tool, as described in the follow-
ing sections.
15.2.1 Spurious LVD Reset after Programming
the Option Bytes
Description
When programming the LVD option from OFF to
ON in ICC mode with Option Bytes enabled (38-
pulse mode) and if the AVD is OFF, a spurious re-
set is generated and ICC communication is lost.
Workaround
At the user level, using the ICC mode with Option
Bytes disabled (35-pulse mode), no spurious reset
is generated.
At the programming tool designer level, either by
generating a reset after or by setting the AVD ON
before programming the Option Bytes, a spurious
LVD reset is avoided.
15.2.2 In-Circuit
Programming
of Devices
Previously
Programmed
with
Hardware
Watchdog Option
Description
In-Circuit Programming of devices configured with
hardware watchdog (WDGSW bit in option byte 1
programmed to 0) requires certain precautions
(see below).
In-Circuit Programming uses ICC mode. In this
mode, the hardware watchdog is not automatically
deactivated as one might expect. As a conse-
quence, internal resets are generated by the
watchdog, thus preventing programming.
The device factory configuration is software
watchdog so this issue is not seen with devices
that are programmed for the first time. For the
same reason, devices programmed by the user
with the software watchdog option are not impact-
ed.
The only devices impacted are those that have
previously been programmed with the hardware
watchdog option.
Workaround
Devices configured with Hardware Watchdog
must be programmed using a specific program-
ming mode that ignores the option byte settings. In
this mode, an external clock, normally provided by
the programming tool, has to be used. In ST tools,
this mode is called "ICP OPTIONS DISABLED".
Sockets on ST programming tools are controlled
using "ICP OPTIONS DISABLED" mode. Devices
can therefore be reprogrammed by plugging them
in the ST Programming Board socket, whatever
the watchdog configuration.
1
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