收藏本站
参数资料
型号： ST7PLITEUS5M6TR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
封装： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件页数： 55/108页
文件大小： 1957K
代理商： ST7PLITEUS5M6TR
ST7LITEUSx
50/108
LITE TIMER (Cont’d)
10.1.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0000 0x00 (0xh)
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
MHz)
Bit 4 = TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog
reset occurred (read).
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hard-
ware at the end of each tWDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
LITE
TIMER
INPUT
CAPTURE
REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Table 16. Lite Timer Register Map and Reset Values
70
ICIE
ICF
TB
TBIE
TBF
WDG
R
WDGE
WDG
D
70
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Address (Hex.) Register Label
7
6
5432
10
0B
LTCSR
Reset Value
ICIE
0
ICF
0
TB
0
TBIE
0
TBF
0
WDGRF
x
WDGE
0
WDGD
0
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
1
相关PDF资料
PDF描述
ST7PLITEUS5M6 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
ST7FLITEUS5M3TR 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
ST7FLITEUS2B3 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP8
ST7FSCR1E4U1 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC64
ST7SCR1T1/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64
相关代理商/技术参数
参数描述
ST7PLITEUS5U3 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with single voltage Flash memory, ADC, timers
ST7PLITEUS5U3TR 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with single voltage Flash memory, ADC, timers
ST7PLITEUS5U6 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with single voltage Flash memory, ADC, timers
ST7PLITEUS5U6TR 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with single voltage Flash memory, ADC, timers
ST7PMC1K2B3 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI?
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*