参数资料
型号: ST7PLUSA2M3
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封装: 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件页数: 109/136页
文件大小: 1705K
代理商: ST7PLUSA2M3
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
On-chip peripherals
ST7LITEUS2, ST7LITEUS5
10.2.5
Interrupts
10.2.6
Register description
Timer control status register (ATCSR)
Reset value: 0000 0000 (00h)
Table 28.
Interrupt events
Interrupt event (1)
1.
The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
Event
flag
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-halt
Overflow event
OVF
OVFIE
Yes
No
Yes(2)
2.
Only if CK0=1 and CK1=0
CMP event
CMPFx
CMPIE
Yes
No
7
0
CK1
CK0
OVF
OVFIE
CMPIE
Read/write
Bits 7:5 Reserved, must be kept cleared.
Bits 4:3 CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset.
They select the clock frequency of the counter (see Table 29: Counter clock
Bit 2 OVF Overflow flag.
This bit is set by hardware and cleared by software by reading the ATCSR register.
It indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms depending on the
clock selection) after it has been cleared by software.
Bit 1 OVFIE Overflow interrupt enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Bit 0 CMPIE Compare interrupt enable.
This bit is read/write by software and clear by hardware after a reset. It allows to
mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
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