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参数资料
| 型号： | ST7PLUSA2M3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 75/136页 |
| 文件大小： | 1705K |
| 代理商： | ST7PLUSA2M3 |
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Obsolete
- Obsolete
Product(s)
Obsolete
- Obsolete
Product(s)
ST7LITEUS2, ST7LITEUS5
Interrupts
43/136
7.4
System integrity management (SI)
The System Integrity Management block contains the low voltage detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 11.2.1: Illegal opcode reset for further details.
7.4.1
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
●
VIT+(LVD) when VDD is rising
●
VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option byte to be low, medium or high. See
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
●
Under full software control
●
In static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Note:
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull VDD down to 0V to ensure optimum restart
conditions. Refer to circuit example in Figure 62 and note 4.
The LVD is an optional function which can be selected by option byte. See Section 14.1 on
page 123. It allows the device to be used without any external RESET circuitry. If the LVD is
disabled, an external circuitry must be used to ensure a proper Power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels
are not correlated. Refer to Table 47 on page 95 and Table 48 on page 96 for more details.
Caution:
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
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