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参数资料
型号： ST7PLUSA2M3
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封装： 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件页数： 125/136页
文件大小： 1705K
代理商： ST7PLUSA2M3
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
ST7LITEUS2, ST7LITEUS5
Instruction set
89/136
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
11.2.1
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
watchdog, allows the detection and recovery from an unexpected fault or interference.
Note:
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Shift and rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional jump or call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
RET
Conditional branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition code flag modification
SIM
RIM
SCF
RCF
Table 41.
ST7 instruction set (continued)
Table 42.
Illegal opcode detection
Mnemo
Description
Function/example
Dst
Src
H
I
N
Z
C
ADC
Add with carry
A = A + M + C
A
M
H
-
N
Z
C
ADD
Addition
A = A + M
A
M
H
-
N
Z
C
AND
Logical and
A = A . M
A
M
-
N
Z
-
BCP
Bit compare A, Memory
tst (A . M)
A
M
-
N
Z
-
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