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参数资料
型号： ST7PLUSA2M3
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封装： 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件页数： 3/136页
文件大小： 1705K
代理商： ST7PLUSA2M3
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
Electrical characteristics
ST7LITEUS2, ST7LITEUS5
100/136
12.4.2
Internal RC oscillator supply current characteristics
Table 53.
Internal RC oscillator supply current
Symbol
Parameter
Conditions
Min
Typ
Max (1)
Unit
IDD
Supply current in Run mode (2)
RC
o
scilla
to
rcali
br
a
te
d
at
5.0V
TA=25 °C, int RC = 4 MHz
3.2
5.5
mA
TA=25 °C, int RC = 8 MHz
5.7
8.5
TA=25 °C, AWU RC
0.13
0.2
Supply current in Wait mode (3)
TA=25 °C, int RC = 4 MHz
1.5
3.0
TA=25 °C, int RC = 8 MHz
1.9
4.5
Supply current in Slow mode (4)
TA=25 °C, int RC/32 = 250 kHz
1.3
2.0
Supply current in Slow-Wait
mode (5)
TA=25 °C, int RC/32 = 250 kHz
1.1
1.8
Supply current in Active-halt
mode
0.8
1.25
IDD
Supply current in Run mode (2)
RC
osci
llator
calib
ra
ted
a
t
3.3
V
TA=25 °C, int RC = 4 MHz
2.0
3.0
mA
TA=25 °C, int RC = 2 MHz
1.3
2.0
TA=25 °C, AWU RC
0.1
0.18
Supply current in Wait mode (3)
TA=25 °C, int RC = 4 MHz
1.0
1.6
TA=25 °C, int RC = 2 MHz
0.9
1.5
Supply current in Slow mode (4)
TA=25 °C, int RC/32 = 250 kHz
0.95
1.5
Supply current in Slow-Wait
mode (5)
TA=25 °C, int RC/32 = 250 kHz
0.85
1.4
Supply current in Active-halt
mode
0.8
1.3
1.
Data based on characterization results, not tested in production.
2.
CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; CPU clock provided by the internal RC, LVD disabled.
3.
All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; CPU clock provided by
the internal RC, LVD disabled.
4.
Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no
load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.
5.
Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS
(no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.
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