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| 型号： | TAS3218IPZPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | GREEN, PLASTIC, TQFP-100 |
| 文件页数： | 33/79页 |
| 文件大小： | 1263K |
| 代理商： | TAS3218IPZPR |
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DSP Instruction Word
55-BIT INSTRUCTION
Ext
ALU First Stage
ALU Second Stage
Data Memory Load
Coefficient Memory Load
Memory Store
0
54
P1OP
53–49
P2OP
48–42
MOP1
AD1
41–37
36–27
MOP2
AD2
23–14
26–24
MOP3
AD3
9–0
13–10
www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008
The key features of the felay memory are
17408 24 delay memory locations
Twenty four separately addressable pointers
Programmable start/stop address on each pointer
Pointers capable of accessing 24-bit or 48-bit words
Single port access (one pointer access per access cycle)
Access cycle < 4 DSP clocks
Self clearing INIT pin used to clear all memory to zero
Fully synchronous
DP1DP15: sixteen 24-bit pointers
RP1RP8: eight 48-bit (full precision) pointers
Since all of the pointers are contiguous, it is only necessary to write the address END point. For example, if DP1
is to be a three-sample delay, the register DP1 should be set to 0x003. If RP1 is to be a 3 sample delay, the
register RP1 should be set to the value of DP15 + 6. All of the DP1-16 and RP1-8registers must be set to a
minimum of a one sample delay (one or two words).
DP1 Start address is defined as 000x0
DP2 Start address is equal to DP1 end address + 1 ...
RP1 Start address is equal to DP16 end address + 1 ...
RP8 Start address is equal to RP7 end address + 2
Since the start/stop address for each pointer is programmable anywhere in the delay RAMs address space, the
delay for any one channel can be anywhere in the delay RAM. There is, however, no address space collision
avoidance logic to separate the pointers. The user (or micro) must take care to avoid overlapping the address
spacing of each pointer.
Pointer register address endpoint registers DP1-DP16 and RP 1-RP8 are typically written only during the
initialization (fast load) mode of the device. Writing to these registers while the TAS3218 DSP core is accessing
the pointers may cause the pointers to cross the address space of another pointer.
To write to the delay RAM, the TAS3218 DSP core controller must present the data to be written on the
PT_DATA bus (LS bit always in bit zero of the bus), select the pointer to be accessed by driving the PT_SEL
pins, and assert the PT_WZ pin for a minimum of four clocks. The pointer will not increment until a write has
been performed and the PT_WZ pin has been de-asserted.
To perform a read, the PT_OUT bus may be read four clocks after PT_SEL is driven.
TAS3218 has a 55-bit instruction word. Each instruction has five independent operations, which can load two
operands from data memory and coefficient memory, store the result into data or coefficient memory and perform
two parallel arithmetic operations.
Figure 30. Instruction Word
The TAS3218 instruction set is a superset of the TAS3218 instruction set, extending the DSP processing
capabilities for improved efficiency of FIR operations as well as extending the addressable memory space. The
Ext instruction bit (bit 54) has been added to extend the internal memory address space by 1 bit, increasing the
memory space from 1K to 2K words.
Copyright 2008, Texas Instruments Incorporated
39
Product Folder Link(s): TAS3218
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