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参数资料
| 型号： | TC59SM808BFTL-70 |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54 |
| 文件页数： | 27/49页 |
| 文件大小： | 2437K |
| 代理商： | TC59SM808BFTL-70 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2001-06-11
33/49
1-7
Read with Auto Precharge command
( RAS = H, CAS = L, WE = H, BS0, BS1 = Bank, A10 = H, A0~A9, A11 = Column Address,
A12=Don't care)
The Read with Auto Precharge command automatically performs the Precharge operation after the
Read operation. When the CAS Latency = 3, the internal precharge starts two cycles before the last
data is output. When the CAS Latency = 2, the internal precharge starts one cycle before the last data
is output (Figure 15). This command must not be interrupted by any other command.
The A11 input is “Don’t care” on the TC59SM808BFT/BFTL and the A9 and A11 inputs are “Don’t care”
on the TC59SM816BFT/BFTL.
1-8
Mode Register Set command
( RAS = L, CAS = L, WE = L, BS0, BS1, A0~A12 = Register Data)
The Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode Register. The default values in the Mode Register after power-up are undefined,
therefore this command must be issued during the power-up sequence. Also, this command can be issued
while all banks are in the idle state.
1-9
No-Operation command
( RAS = H, CAS = H, WE = H)
The No-Operation command simply performs no operation.
1-10 Burst stop command
( RAS = H, CAS = H, WE = L)
The Burst stop command is used to stop the burst operation. This command is valid during a Full Page
Burst operation. During other types of Burst operation, the command is illegal.
1-11 Device Deselect command
( CS = H)
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
1-12 Auto Refresh command
( RAS = L, CAS = L, WE = H, CKE = H, BS0, BS1, A0~A12 = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh counter.
The Refresh operation must be performed 8192 times within 64 ms. The next command can be issued
after tRC from the end of the Auto Refresh command. When the Auto Refresh command is issued, All
banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS -before- RAS
operation in a conventional DRAM.
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