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参数资料
| 型号： | TC59SM808BFTL-70 |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54 |
| 文件页数： | 33/49页 |
| 文件大小： | 2437K |
| 代理商： | TC59SM808BFTL-70 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2001-06-11
39/49
Addressing sequence example (Burst Length
= 8 and input address is 13.)
Interleave Mode
Sequential Mode
DATA
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADD
Data0
0
1
0
1
13
Data1
0
1
0
12
13
+ 1
14
Data2
0
1
15
13
+ 2
15
Data3
0
1
0
14
13
+ 3
8
Data4
0
1
0
1
9
13
+ 4
9
Data5
0
1
0
8
13
+ 5
10
Data6
0
1
0
1
11
13
+ 6
11
Data7
0
1
0
1
0
10
13
+ 7
12
calculated using
A2, A1 and A0 bits
not carry from
A2 to A3 bit.
CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data
read. The minimum values of CAS Latency depends on the frequency of CLK. The minimum value which
satisfies the following formula must be set in this field.
A6
A5
A4
CAS
Latency
0
1
0
2 clock
0
1
3 clock
Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to 0 for normal operation.
Reserved bits (A8, A10, A11, A12, BS0, BS1)
These bits are reserved for future operations. They must be set to 0 for normal operation.
Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are
selected. When the A9 bit is 1, Burst Read and Single Write mode are selected.
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
Read Cycle CAS Latency
= 3
Command
Read
13
0
1
2
3
4
5
6
7
8
9
10
11
DQ0~DQ7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Address
Data
Address
Interleave mode
13
12
15
14
9
8
11
10
13
14
15
8
9
10
11
12
Sequential mode
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