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参数资料
| 型号： | TC59SM808BFTL-70 |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54 |
| 文件页数： | 48/49页 |
| 文件大小： | 2437K |
| 代理商： | TC59SM808BFTL-70 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2001-06-11
8/49
(8)
These parameters account for the number of clock cycles and depend on the operating frequency of the
clock, as follows:
the number of clock cycles = specified value of timing / clock period
(count fractions as a whole number)
(9)
Power-up Sequence
Power-up must be performed in the following sequence.
1)
Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the
“NOP” state. The CLK signals must be started at the same time.
2)
After power-up a pause of at least 200 s is required. It is required that DQM and CKE signals
must be held “High” (VCC levels) to ensure that the DQ output is in High-impedance state.
3)
All banks must be precharged.
4)
The Mode Register Set command must be asserted to initialize the Mode Register.
5)
A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of
the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
(10)
AC Latency Characteristics
CKE to clock disable (CKE Latency)
1
DQM to output in High-Z (Read DQM Latency)
2
DQM to input data delay (Write DQM Latency)
0
Write command to input data (Write Data Latency)
0
CS
to Command input ( CS Latency)
0
CL
= 2
2
Precharge to DQ Hi-Z Lead time
CL
= 3
3
CL
= 2
1
Precharge to Last Valid data out
CL
= 3
2
CL
= 2
2
Burst Stop Command to DQ Hi-Z Lead time
CL
= 3
3
CL
= 2
1
Burst Stop Command to Last Valid data out
CL
= 3
2
Cycle
CL
= 2
BL
+ tRP
Read with Autoprecharge Command to Active/Ref Command
CL
= 3
BL
+ tRP
CL
= 2
BL
+ tRP
Write with Autoprecharge Command to Active/Ref Command
CL
= 3
BL
+ tRP
Cycle
+ ns
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