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参数资料
| 型号： | TLV320AIC22PTR |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | Codec |
| 英文描述： | DUAL VOIP CODEC |
| 中文描述： | 双VoIP编解码器 |
| 文件页数： | 18/55页 |
| 文件大小： | 763K |
| 代理商： | TLV320AIC22PTR |
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TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
address pins description (continued)
Table 5. AD0 and AD1 vs Time-Slot Assignment
TLV320AIC22
DEVICE
AD1
AD0
TIME SLOT
CODEC 1
TIME SLOT
CODEC 2
0
2
3
1
0
1
4
5
2
1
0
6
7
3
1
8
9
This address description also is used to make the codec register address map unique across the codecs. This
is explained further below.
master/slave functionality
The TLV320AIC22 can be configured as a master or a slave. A particular codec is configured as the master by
tying the M/S pin (pin 21) high. Tying this pin low configures the device as a slave.
This functionality can be used for connecting multiple TLV320AIC22 devices to a single MCBSP port. See
Figure 20 for details. Only one device can be a master in such a system. The master device generates the
FSYNC and the BCLK signals that are used by the DSP and the remaining TLV320AIC22s in the system. The
slave devices input the FSYNC and BCLK signals generated by the master device.
The TLV320AIC22 also can be used as a stand-alone slave. In this configuration, there is no master
TLV320AIC22 device providing the FSYNC and BCLK signals. FSYNC and BCLK are provided by some other
device, such as a DSP or ASIC.
Careful attention must be paid to the relationship between MCLK, FSYNC, and BCLK when using stand-alone
slave configurations. When operating the device in the default mode (sampling-rate mode-1 configuration), the
configurations shown in Table 6 must be met.
Table 6. Slave-Mode Clock Inputs
MCLK INPUT
FREQUENCY
BCLK INPUT
FREQUENCY
FSYNC INPUT
FREQUENCY
REGISTER 12
VALUE (BITS
D6–D4, DECIMAL)
24.576 MHz
2.048 MHz
8 kHz
0
24.576 MHz
4.096 MHz
16 kHz
2
32.768 MHz
2.048 MHz
8 kHz
1
32.768 MHz
4.096 MHz
16 kHz
3
All of these signals (BCLK, MCLK, and FSYNC) must be synchronous. The appropriate values for register 12,
bits D6 – D4, as well as the I values for codec 1 (register 2) and codec 2 (register 7), must be loaded prior to
transmitting and receiving valid conversion data to obtain the desired sampling rate. See the channel sampling
rates section for a detailed description.
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