参数资料
型号: TLV320AIC22PTR
厂商: Texas Instruments, Inc.
元件分类: Codec
英文描述: DUAL VOIP CODEC
中文描述: 双VoIP编解码器
文件页数: 8/55页
文件大小: 763K
代理商: TLV320AIC22PTR
TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
codecs
There are two codecs on the TLV320AIC22 that can be connected to any of the analog inputs or outputs via
the internal analog crosspoint. The codecs are full 8-bit PCM companded or 16-bit linear codecs that meet G.711
standards and include transmit band-pass and receive low-pass filters. A-law/
-law companding or linear
coding and –36 dB to 12 dB of analog gain adjustment in steps of 1.5 dB for each path are selectable via the
I2C or serial interface. These modes can be selected by programming the appropriate register. In the 8-bit PCM
companded mode, the data is zero padded to 15 bits, and the 16th bit serves as the valid data bit.
analog crosspoint
The internal analog crosspoint is a lossless analog switch matrix controlled via the I2C or serial interface. It
allows any source device to be connected to any sink device. Additionally, special summing connections with
adjustable loss are included to implement sidetone for the handset and headset ports. A muting function is
included on any of the sink devices. The control for the analog crosspoint, defined in the register map, is done
in such a way that a particular analog input or output can be connected to a codec by setting a single bit. This
implies that more than one analog input or output can be connected to a codec at one time. Full performance
is assured for two or fewer inputs and outputs connected to a codec, except in the case of the line output.
Connecting the output of both codecs to the line output (LNOUTP and LNOUTM) is not allowed.
ADC channel
The ADC channel consists of a programmable gain amplifier (PGA), antialiasing filter, sigma-delta ADC and
decimation filter. The ADC is an oversampling sigma-delta modulator. The ADC provides high resolution and
low-noise performance using oversampling techniques and the noise-shaping advantages of sigma-delta
modulators.
The analog input signals are amplified and filtered by on-chip buffers and an antialiasing filter before being
applied to ADC input. The ADC converts the signal into discrete output digital words, in 2s-complement format,
corresponding to the analog signal value at the sampling time.
The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating with
a ratio equal to the oversampling ratio. The output of this filter is a 15-bit 2s-complement data word, clocking
at the selected sample rate. The sixteenth bit is a data-valid flag.
These 15-bit digital words, representing sampled values of the analog input signal, are sent to the host via the
serial-port interface. If the ADC reaches its maximum value, a control register flag is set. This bit can be read
only via the serial port. The ADC and DAC conversions are synchronous.
The digital conversion data is transmitted out of the device via the serial interface, with the data-valid flag being
transmitted first, followed by the MSB of the conversion data. Data is transmitted on the rising edge of BCLK.
The bandwidth of the codec is 3.6 kHz, for a sampling rate of 8 kHz, and scales linearly for other sampling rates.
The gain of the ADC input amplifier is programmed in register 3 for codec 1 and register 8 for codec 2.
The ADC channel contains a high-pass filter that suppresses power-line frequencies that can be bypassed by
programming the appropriate bits in registers 15 and 16 for codec 1 or codec 2, respectively.
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