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参数资料
型号： TLV320AIC22PTR
厂商： Texas Instruments, Inc.
元件分类： Codec
英文描述： DUAL VOIP CODEC
中文描述： 双VoIP编解码器
文件页数： 45/55页
文件大小： 763K
代理商： TLV320AIC22PTR
TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
HSINM
40
I
Handset amplifier analog inverting input. A connection between HSIN and HSOUT occurs, with selected echo
gain, unless the echo gain is muted. See register 13.
HSINP
41
I
Handset amplifier analog noninverting input. A connection between the HSIN and HSOUT occurs, with
programmed echo gain, unless the echo gain is muted. See register 13.
HSOUTM
38
O
Inverting handset output. The HSOUTM pin, together with the HSOUTP pin forms the differential output. With
HSOUTP, a 150-
load can be driven differentially. HSOUTM also can be used alone for single-ended operation.
HSOUTP
39
O
Noninverting handset output. With HSOUTM, a 150-
load can be driven, differentially. HSOUTP also can be
used alone for single-ended operation.
I2C/SPI
14
I
I2C/serial port interface select. Setting this pin high allows the user to program the registers using the I2C
interface. A low state configures the serial interface to be used for control register programming during normal
data transmission using time slots 0 and 1. When set high (I2C interface selected) time slots 0 and 1 in the normal
data transmission are ignored.
LCDOUT
37
O
4-bit DAC output voltage, programmed through the control interface. This can be used to provide the bias voltage
for an LCD display.
LNINP
44
I
Line-port amplifier analog noninverting input. See Note 4.
LNINM
45
I
Line-port amplifier analog inverting input. See Note 4.
LNOUTM
46
O
Inverting line-port output. The LNOUTM pin, together with the LNOUTP pin, forms the differential output. With
LNOUTP, a 600-
load can be driven differentially. LNOUTM also can be used alone for single-ended operation.
See Note 4.
LNOUTP
47
O
Noninverting line-port output. With LNOUTM, a 600-
load can be driven, differentially. LNOUTP also can be
used alone for single-ended operation. See Note 4.
MCLK
22
I
Master clock input. All internal clocks are derived from this clock. This clock typically is 32.768 MHz or
24.576 MHz.
MCBIAS
36
O
MCBIAS provides a bias voltage and current to operate Electret microphones. The bias voltage is specified
across the microphone at 2.5 V.
MCINM
34
I
Microphone amplifier analog inverting input
MCINP
35
I
Microphone amplifier analog noninverting input
M/S
21
I
Master/slave select input. When M/S is high, the device is the master, and when it is low, it is a slave.
PWRDWN
9
I
Power down. PWRDWN is active high. When PWRDWN is pulled high, the device goes into a power-down mode,
and the output drivers and most of the high-speed clocks are disabled. The serial interface and I2C interface are
enabled. However, all register values are sustained and the device resumes full-power operation without
reinitialization when PWRDWN is pulled low again. PWRDWN resets the counters only and preserves the
programmed register contents.
RESET
23
I
Codec device reset. RESET initializes all device internal registers to default values. This signal is active low.
SCL
11
I
SCL is the serial control interface clock for the I2C interface, and is used to clock control bits into and out of the
device through the SDA pin. Tie this pin to DVDD when not used.
SDA
10
I/O
Bidirectional control data I/O line for the I2C interface. Data is clocked into and out of the device by SCL. Tie this pin
to DVDD when not used.
SPOUTP
26
O
Inverting analog output from 8-
speaker amplifier
SPOUTM
28
O
Noninverting analog output from 8-
speaker amplifier
NC
7, 8
Reserved. Leave unconnected.
VCOM
48
O
VCOM provides a reference voltage of 1.5 V. The maximum source or sink current at this terminal is 2.5 mA.
VSS
24
I
Internal substrate connection. VSS should be tied to AVSS1 and AVSS2. See Note 3.
NOTES:
3. This device has separate analog and digital power and ground pins. For best operation and results, the PC board design should
utilize separate analog and digital power supplies as well as separate analog and digital ground planes. Mixed-signal design
practices should be used.
4. The LNINP and LNINM are sensitive to crosstalk from LNOUTP and LNOUTM. Keep the LNOUT and LNIN signals separated on
the printed circuit board. Do not route the LNOUT signals parallel to the LNIN signals.
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