参数资料
型号: TLV320AIC32IRHB
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封装: 5 X 5 MM, PLASTIC, QFN-32
文件页数: 14/76页
文件大小: 1124K
代理商: TLV320AIC32IRHB
www.ti.com
BCLK
WCLK
SDIN/
SDOUT
n2 n3
1
0
n1 n2
1
0
1/fs
LSB
MSB
Left Channel
Right Channel
n1
MSB
LSB
n4
2
n3
2
MSB
LSB
TDM DATA TRANSFER
N-1
N-2
1
0
N-1
N-2
1
0
word
clock
bit clock
data
in/out
RightChannelData
LeftChannelData
N-1
N-2
1
0
N-1
N-2
1
0
word
clock
bit clock
data
in/out
DSP Mode
LeftJustifiedMode
offset
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
OVERVIEW (continued)
Figure 22. DSP Serial Bus Mode Operation
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit
clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to tri-state during all bit clocks except when valid data
is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their
data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the
bus except where it is expected based on the programmed offset.
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other
in the frame. This differs from left-justified mode, where the left and right channel data will always be a
half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both
the left and right channel data move across the frame, but still stay a full half-frame apart from each other. This
is depicted in Figure 23 for the two cases.
Figure 23. DSP Mode and Left Justified Modes, Showing the
Effect of a Programmed Data Word Offset
21
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