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参数资料
| 型号： | TLV320AIC32IRHB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件页数： | 9/76页 |
| 文件大小： | 1124K |
| 代理商： | TLV320AIC32IRHB |
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OVERVIEW
HARDWARE RESET
DIGITAL CONTROL SERIAL INTERFACE
I2C CONTROL INTERFACE
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
The TLV320AIC32 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended
for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
Available in a 5 x 5 mm, 32-lead QFN, the product integrates a host of features to reduce cost, board space,
and power consumption in space-constrained, battery-powered, portable applications.
The TLV320AIC32 consists of the following blocks:
Stereo audio multi-bit delta-sigma DAC (8 kHz – 96 kHz)
Stereo audio multi-bit delta-sigma ADC (8 kHz – 96 kHz)
Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, de-emphasis)
Six audio inputs
Four high-power audio output drivers (headphone/speaker drive capability)
Three fully differential line output drivers
Fully programmable PLL
Headphone/headset jack detection with interrupt
The TLV320AIC32 requires a hardware reset after power-up for proper operation. After all power supplies are at
their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the 'AIC32 may not respond properly to register reads/writes.
The register map of the TLV320AIC32 actually consists of multiple pages of registers, with each page containing
128 registers. The register at address zero on each page is used as a page-control register, and writing to this
register determines the active page for the device. All subsequent read/write operations will access the page
that is active at the time, unless a register write is performed to change the active page. Only two pages of
registers are implemented in this product, with the active page defaulting to page 0 upon device reset.
For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for
addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write
the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page
1. After this write, it is recommended the user also read back the page control register, to safely ensure the
change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now
access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence
0x00 to register 0, the page control register, to change the active page back to page 0. After a recommended
read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0
registers again.
The TLV320AIC32 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving them LOW.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction
of the master. Some I2C devices can act as masters or slaves, but the TLV320AIC32 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the
appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit
into the receivers shift register.
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相关代理商/技术参数 |
参数描述 |
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| TLV320AIC32IRHBG4 | 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 32BIT 32QFN EP - Rail/Tube |
| TLV320AIC32IRHBR | 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC32IRHBRG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC32IRHBT | 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC32IRHBTG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
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