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参数资料
| 型号： | TLV320AIC32IRHB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件页数： | 16/76页 |
| 文件大小： | 1124K |
| 代理商： | TLV320AIC32IRHB |
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www.ti.com
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
OVERVIEW (continued)
The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK
input can also be used to generate the internal audio master clock.
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations
easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with
particular focus paid to the standard MCLK rates already widely used.
When the PLL is disabled,
Fsref = CLKDIV_IN / (128
× Q)
Where Q = 2, 3,
…, 17
CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7-D6.
NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as
high as 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.
When the PLL is enabled,
Fsref = (PLLCLK_IN
× K × R) / (2048 × P), where
P = 1, 2, 3,
…, 8
R = 1, 2,
…, 16
K = J.D
J = 1, 2, 3,
…, 63
D = 0000, 0001, 0002, 0003,
…, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz
≤ ( PLLCLK_IN / P ) ≤ 20 MHz
80 MHz
≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz
4
≤ J ≤ 55
When the PLL is enabled and D
≠0000, the following conditions must be satisfied to meet specified performance:
10 MHz
≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz
≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4
≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and Fsref = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and Fsref = 48.0 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
23
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| TLV320AIC32IRHBT | 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
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