参数资料
型号: TMS320VC5409PGE-80
厂商: Texas Instruments
文件页数: 25/93页
文件大小: 0K
描述: IC FIXED POINT DSP 144-LQFP
标准包装: 60
系列: TMS320C54x
类型: 定点
接口: 主机接口,McBSP
时钟速率: 80MHz
非易失内存: ROM(32 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.80V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
31
April 1999 Revised October 2008
SPRS082F
3.3.1.3.1 Host Bus Holder Configuration
The 5409 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of
the address bus (A[150]), data bus (D[150]) and the HPI data bus (HD[70]). The bus keeper
enabling/disabling is described in Table 5.
Table 36. Bus Holder Control Bits
HPI16 pin
BH
HBH
D[150]
A[150]
HD[70]
0
OFF
0
1
OFF
ON
0
1
0
ON
OFF
0
1
ON
OFF
ON
1
0
OFF
ON
1
0
1
OFF
ON
1
0
ON
OFF
ON
1
ON
The HPI bus holders are activated via the HBH bit in the Bank Switch Control Register (BSCR). The HBH bit
can control bus holder behavior for both the 8-bit and 16-bit modes. In the 8-bit mode, the HBH bit controls
the bus holders on the host data pins HD7HD0. When HBH = 1, the host data bus holders are active. When
HBH = 0 the host data bus holders are inactive. In the 16-bit nonmultiplexed mode, the bus holders for pins
HD7HD0 are always active; however, the HBH bit controls the host address pins A15A0. When HBH = 1,
the host address bus holders are active. When HBH = 0, the host address bus holders are inactive.
3.3.1.4
Operation During IDLE2
The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns
on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.
The DSP CPU does not wake up from the IDLE mode during this process.
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