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| 型号： | TMS320VC5409PGE-80 |
| 厂商： | Texas Instruments |
| 文件页数： | 27/93页 |
| 文件大小： | 0K |
| 描述： | IC FIXED POINT DSP 144-LQFP |
| 标准包装： | 60 |
| 系列： | TMS320C54x |
| 类型： | 定点 |
| 接口： | 主机接口，McBSP |
| 时钟速率： | 80MHz |
| 非易失内存： | ROM（32 kB） |
| 芯片上RAM： | 64kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
| 配用： | 296-15829-ND - DSP STARTER KIT FOR TMS320C5416 |
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Functional Overview
33
April 1999 Revised October 2008
SPRS082F
Table 37. Pin Control Register (PCR) Bit Field Description
BIT
NAME
FUNCTION
15 – 14
Reserved
Reserved. Pins are not used.
13
XIOEN
Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)
XIOEN = 0
DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os.
XIOEN = 1
DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These serial port
pins do not perform serial port operations.
12
RIOEN
Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)
RIOEN = 0
DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not general-purpose
I/Os.
RIOEN = 1
DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose I/Os.
These serial port pins do not perform serial port operations. The CLKS pin is affected by a
combination of RRST and RIOEN signals of the receiver.
11
FSXM
Transmit frame synchronization mode
FSRM = 0
Frame synchronization signal derived from an external source.
FSRM = 1
Frame synchronization is determined by the sample rate generator frame synchronization mode
bit (FSGM) in the SRGR2.
10
FSRM
Receive frame synchronization mode
FSRM = 0
Frame synchronization pulses generated by an external device. FSR is an input pin.
FSRM = 1
Frame synchronization generated internally by the sample rate generator. FSR is an output pin
except when GSYNC=1 in the SRGR.
9
CLKXM
Transmitter clock mode
CLKXM = 0
Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input pin
CLKXM= 1
CLK(R/X) is an output pin and is driven by the internal sample rate generator
During SPI mode (CLKSTP is a non-zero value):
CLKXM = 0
McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR is
internally driven by CLKX.
CLKXM= 1
McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the
shift clock of the SPI-compliant slaves in the system.
8
CLKRM
Receiver clock mode
Case 1: Digital loop-back mode is not set (DLB=0) in SPCR1.
CLKRM = 0
Receive clock (CLKR) is an input pin driven by an external clock.
CLKRM= 1
CLKR is an output pin and is driven by the internal sample rate generator
Case 2: Digital loop-back mode set (DLB=1) in SPCR1
CLKRM = 0
Receive clock (Not the CLKR pin) is driven by transmit clock (CLKX), which is based on CLKXM
bit in the PCR. CLKR pin is in high-impedance mode.
CLKRM= 1
CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based
on the CLKXM bit in the PCR.
7
SCLKME
Sample rate clock mode extended
SCLKME = 0
External clock via CLKS or CPU clock is used as a reference by the sample rate generator.
SCLKME = 1
External clock via CLKR or CLKX clock is used as a reference by the sample rate generator.
6
CLKS STAT
CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.
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