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| 型号： | TMS320VC5409PGE-80 |
| 厂商： | Texas Instruments |
| 文件页数： | 9/93页 |
| 文件大小： | 0K |
| 描述： | IC FIXED POINT DSP 144-LQFP |
| 标准包装： | 60 |
| 系列： | TMS320C54x |
| 类型： | 定点 |
| 接口： | 主机接口，McBSP |
| 时钟速率： | 80MHz |
| 非易失内存： | ROM（32 kB） |
| 芯片上RAM： | 64kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
| 配用： | 296-15829-ND - DSP STARTER KIT FOR TMS320C5416 |
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Introduction
17
April 1999 Revised October 2008
SPRS082F
Table 22. Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O
INTERNAL
TERMINAL
NAME
DESCRIPTION
I/O
PIN STATE
MEMORY CONTROL SIGNALS (CONTINUED)
HOLDA
O/Z
Hold acknowledge. HOLDA indicates that the 5409 is in a hold state and that the address, data, and
control lines are in the high-impedance state, allowing the external memory interface to be
accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low. This
pin is driven high during reset.
MSC
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more
software wait states are enabled, the MSC pin goes low during the last of these wait states. If
connected to the READY input, MSC forces one external wait state after the last internal wait state
is completed. MSC also goes into the high-impedance state when OFF is low.
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on
the address bus. IAQ goes into the high-impedance state when OFF is low.
OSCILLATOR/TIMER SIGNALS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal
machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the
high-impedance state when OFF is low.
CLKMD1
CLKMD2
CLKMD3
Schmitt
trigger
I
Clock mode select signals. These inputs select the mode that the clock generator is initialized to
after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the
clock mode register is initialized to the selected mode. After reset, the clock mode can be changed
through software, but the clock mode select signals have no effect until the device is reset again.
X2/CLKIN
Schmitt
trigger
I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock
input.
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should
be left unconnected. X1 does not go into the high-impedance state when OFF is low.
TOUT
O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is
one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1
BCLKR2
Schmitt
trigger
I/O/Z
Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input
from an external clock source for clocking data into the McBSP. When not being used as a clock,
these pins can be used as general-purpose I/O by setting RIOEN = 1.
BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.
BDR0
BDR1
BDR2
I
Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can
be used as general-purpose I/O by setting RIOEN = 1.
BFSR0
BFSR1
BFSR2
I/O/Z
Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the
receive-data process over the BDR pin. When not being used as data-receive synchronization pins,
these pins can be used as general-purpose I/O by setting RIOEN = 1.
BCLKX0
BCLKX1
BCLKX2
Schmitt
trigger
I/O/Z
Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be
configured as an input by setting the CLKXM = 0 in the PCR register. When not being used as a
clock, these pins can be used as general-purpose I/O by setting XIOEN = 1.
These pins are placed into the high-impedance state when OFF is low.
I = Input, O = Output, Z = High-impedance, S = Supply
Although this pin includes an internal pulldown resistor, a 470- external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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