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| 型号： | TPS51020EVM-001 |
| 厂商： | Texas Instruments |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR TPS51020-001 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 3.3V，5V |
| 电流 - 输出： | 6A，6A |
| 输入电压： | 8 ~ 20 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | TPS51020 |
| 产品目录页面： | 1028 (CN2011-ZH PDF) |
| 相关产品： | TPS51020DBTRG4-ND - IC DUAL DC/DC SYNC CTRLR 30TSSOP 296-26971-2-ND - IC DUAL DC/DC SYNC CTRLR 30TSSOP TPS51020DBTG4-ND - IC DUAL DC/DC SYNC CTRLR 30TSSOP 296-15896-5-ND - IC DUAL DC/DC CTRLR SYNC 30TSSOP |
| 其它名称： | 296-18958 |
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TPS51020
SLUS564C ? JULY 2003 ? REVISED OCTOBER 2008
APPLICATION INFORMATION
If one channel is enabled in the period between T0 and T1, (the other channel’s ramp time plus delay time,) the
PGOOD delay counter restarts counting softstart finish after the last channel has finished softstart. Enabling
after T1 is ignored by PGOOD until the channel finishes its softstart. If either of the SMPS output goes out by
± 7.5% or UVLO is detected while ENBLx is high, PGOOD pulls low. If a channel is disabled while the other is
still active PGOOD maintains it’s logic state and only monitor the active channel.
PROTECTION FUNCTIONS
The TPS51020 is equipped with input undervoltage lock out (UVLO), output undervoltage protection (UVP) and
overvoltage (OVP) protection. Overcurrent is detected using R DS(on) of the external power MOSFETs and
protected by triggering UVP, or latch off in some cases. The states of output drive signal depends on which
protection was involved. Please refer to each protection description below for the detail.
When the input voltage UVLO is tripped, the TPS51020 resets and waits for the voltage to rise up over the
threshold voltage and restart the device. Alternatively, if output UVP or OVP is triggered, the device latches off
after a delay time defined by the internal fault counter counting the PWM oscillator pulses. The VREF5 and
REF_X is kept on in this latch off condition. The fault latch can be reset by toggling both of ENBLx pins in DDR
mode. The fault latch can be reset by either toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure
to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode.
If a false trip of the UVLO appears due to input voltage sag during turn-on of the high-side MOSFET such as
a large load transient, first consider adding several micro-farads of input capacitance close to the MOSFET’s
drain. Also consider adding a small V IN filter, ex. a 2.2- ? resistor and a 2.2- μ F, for decoupling. The trip resistors
should be connected to the same node as VIN pin of the device when this filter is applied. The filter resistor
should be as small as possible since a voltage drop across this resistor biases the OCP trip point.
UNDERVOLTAGE LOCKOUT PROTECTION
There are two undervoltage lock out protections (UVLO) in TPS51020. One is for V IN , which has a typical trip
threshold voltage 3.9 V and trip hysteresis 200 mV. The other is for VREF5, which has a typical trip threshold
voltage 3.65 V and trip hysteresis 300 mV. If either is triggered, the device resets and waits for the voltage to
rise up over the threshold voltage and restart the part. Please note this protection function DOES NOT trigger
the fault counter to latch off the part.
OVERVOLTAGE PROTECTION
For overvoltage protection (OVP), the TPS51020 monitors INVx voltage. When the INVx voltage is higher than
0.95V (+12%), the OVP comparator output goes high (after a 20- μ s delay) and the circuit latches the top
MOSFET driver OFF, and bottom driver ON for the SMPS detected overvoltage. In addition, the output
discharge (softstop) function is enabled to discharge the output capacitor. The fault latch can be reset by either
toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when
TPS51020 is being used in dual mode.
UNDERVOLTAGE PROTECTION
For undervoltage protection (UVP), the TPS51020 monitors INVx voltage. When the INVx voltage is lower than
0.55 V (?35 %), the UVP comparator output goes high, and the internal FLT timer starts to count PWM oscillator
pulses. After 4096 clock pulses, the part latches off. Both top and bottom drivers are turned off at this condition.
Output discharge (soft-stop) function is enabled to discharge the output capacitor. The fault latch can be reset
by either toggling VIN or bringing DDR, ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx
when TPS51020 is being used in dual mode.
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