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参数资料
| 型号： | TPS65181RGZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQCC48 |
| 封装： | 7 X 7 MM, 0.90 MM HEIGHT, GREEN, PLASTIC, VQFN-48 |
| 文件页数： | 10/41页 |
| 文件大小： | 892K |
| 代理商： | TPS65181RGZR |
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SLVSA76F
– MARCH 2010 – REVISED FEBRUARY 2011
additional temperature reading the same way as for the TPS65180/TPS65180B. Please note that at the end of
each temperature acquisition the EOC interrupt will be set and an interrupt will be issued. Although the interrupt
is automatically cleared, the nINT pin will be pulled low for a short amount of time (6
s). To avoid seeing the
EOS interrupt every 60s it is recommended to mask the EOC interrupt by setting the EOC_EN bit of the
INT_ENABLE2 register to 0.
OVER TEMPERATURE REPORTING
The user has the option of setting HOT and COOL (not HOT) temperature thresholds as well as controlling
interrupt behavior as the NTC exceeds HOT and cools down below COOL (not-HOT) threshold.
By default, TPS65180/TPS65181 and TPS65180B/TPS65181B compare the temperature conversion result to the
HOT threshold after each conversion. If the NTC temperature is above the HOT threshold, the TMST_HOT bit in
the INT_STATUS1 register is set to 1 and the interrupt pin (nINT) is pulled low. HOT temperature threshold is set
by the host by writing to the TMST_OS register and the HOT interrupt can be disabled by setting the HOT_EN bit
of the INT_ENABLE1 register to 0.
Once the device has detected that the NTC is above the HOT threshold it will compare subsequent temperature
acquisitions against the COOL threshold and pull the interrupt pin low when the NTC temperature drops below
the COOL threshold. However, the interrupt will be issued only if the host has unmasked the COOL interrupt by
setting TMST_COOL_EN bit of INT_ENABLE1 register to 1. The COOL threshold is set by the host by writing to
the TMST_HYST register.
To use the full functionality of the HOT/COOL interrupts the following actions are required:
1. The host sets the HOT and COOL (not HOT) thresholds by writing the TMST_OS and TMST_HYST
registers.
2. (2) For TPS65180/TPS65180B only: The host sets the READ_THERM bit of the TMST_CONFIG register to
‘1’. This initiates the temperature acquisition.
3. TPS65180/TPS65181 and TPS65180B/TPS65181B compare the result against the TMST_OS threshold and
will pull the nINT pin low if the NTC temperature exceeds the HOT threshold.
4. If the TPS65180/TPS65181 and TPS65180B/TPS65181B report a HOT condition, the host unmasks the
TMST_COOL_EN bit by setting it to 1 (INT_ENABLE1 register).
5. The host initiates a new temperature conversion by setting the READ_THERM bit of the TMST_CONFIG
register to 1. If the new temperature is still above the HOT threshold, a new HOT interrupt will be issued. If
the temperature is below HOT but above COOL threshold, no interrupt is issued (except for EOC which is
issued at the end of each conversion). If the temperature is below COOL threshold, a COOL interrupt is
issued.
6. After the temperature drops below the COOL threshold the host should set the TMST_COOL_EN bit in the
INT_ENABLE1 register to 0 to mask additional COOL interrupts after subsequent temperature acquisitions.
OVER-TEMPERATURE FAULT QUEUING
The user can specify the number of consecutive HOT temperature reads required to issue a HOT interrupt. The
user can set the FAULT_QUE[1:0] bits of the TMST_CONFIG register to specify 1, 2, 4, or 6 consecutive reads
that all must be above the HOT threshold before a HOT interrupt is issued. The fault queue is reset each time
the acquired temperature drops below the HOT threshold and can also be reset by the host by setting the
FAULT_QUE_CLR bit 1. Only if the specified number of readings have been detected which all need to be above
the HOT threshold, a HOT interrupt is issued. This function is useful to reduce noise in the temperature
measurements.
TPS65181/TPS65181B TEMPERATURE SENSOR
The TPS65181/TPS65181B automates the temperature monitoring process and is specifically designed to
operate in multi-host systems where one of the I2C hosts, e.g. the display controller, has limited I2C capability.
Standard I2C protocol requires the following steps to read data from a register:
1. Send device and register address, R/nW bit set low (write command).
2. Send device address, R/nW set high (read command).
3. The slave will respond with data from the specified register address.
Some display controllers support I2C read commands only and need to access the temperature data from the
18
2010–2011, Texas Instruments Incorporated
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