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参数资料
| 型号： | TPS65181RGZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQCC48 |
| 封装： | 7 X 7 MM, 0.90 MM HEIGHT, GREEN, PLASTIC, VQFN-48 |
| 文件页数： | 13/41页 |
| 文件大小： | 892K |
| 代理商： | TPS65181RGZR |
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S
A6 A5 A4 A3 A2 A1 A0
A
S7 S6 S5 S4 S3 S2 S1 S0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
S
A
Start Condition
Acknowledge
A6
A0
...
Device Address
R/nW
Read / not Write
S7
S0
...
Sub-Address
D7
D0
...
Data
P
Stop Condition
R/nW
Slave Address + R/nW
Sub Address
Data
SLVSA76F
– MARCH 2010 – REVISED FEBRUARY 2011
At system power-up the main processor sets up the PMIC by accessing the I2C registers and setting the control
parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit
and the display controller can start accessing the temperature information. During normal operation the main
controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit
must be written 0.
I
2C BUS OPERATION
The TPS65180/TPS65181 and TPS65180B/TPS65181B host a slave I2C interface that supports data rates up to
400 kbit/s and auto-increment addressing and is compliant to I2C standard 3.0.
Figure 6. Subaddress in I2C Transmission
Start
– Start condition
ACK
– Acknowledge
G(3:0)
– Group ID: Address fixed at 1001.
S(7:0)
– Subaddress: defined per register map.
A(2:0)
– Device Address: Address fixed at 000.
D(7:0)
– Data; Data to be loaded into the device.
R/nW
– Read / not Write Select Bit
Stop
– Stop condition
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open Drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 8. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. The I2C interface will auto-sequence through register addresses, so that multiple
data words can be sent for a given I2C transmission. Reference Figure 8. Please note that auto-increment is not
supported when the FIX_RD_PTR bit is set (TPS65181/TPS65181B only).
20
2010–2011, Texas Instruments Incorporated
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