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参数资料
| 型号： | TPS65181RGZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQCC48 |
| 封装： | 7 X 7 MM, 0.90 MM HEIGHT, GREEN, PLASTIC, VQFN-48 |
| 文件页数： | 5/41页 |
| 文件大小： | 892K |
| 代理商： | TPS65181RGZR |
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DLY1
DLY2
DLY3
STROBE 1
SEQ = 00
STROBE 2
SEQ = 01
STROBE 3
SEQ = 10
STROBE 4
SEQ = 11
WAKEUP
DLY0 + 5.5ms
DLY3
DLY2
DLY1
STROBE 4
SEQ = 11
STROBE 3
SEQ = 10
STROBE 2
SEQ = 01
STROBE 1
SEQ = 00
WAKEUP
DLY0
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first
strobe to occur after WAKEUP has been pulled high and STROBE4 is the last event in the sequence.
STROBES are assigned to rails in PWR_SEQ0 register and delays between states are defined in
PWR_SEQ1 and PWR_SEQ2 registers.
BOTTOM: Power-down sequence follows reverse power-up sequence.
SLVSA76F
– MARCH 2010 – REVISED FEBRUARY 2011
Figure 2. I2C Control
DEPENDENCIES BETWEEN RAILS
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are listed below.
1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power good.
2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power-good.
3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is
gated by DCDC1 power good.
4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power good.
5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power good.
6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power
good.
7. The minimum delay time between any two PWRx pins must be
> 62.5 s in order to follow the power up
sequence defined by GPIO control. If any two PWRx pins are pulled up together (
< 62.5 s apart) or the
sequencer tries to bring up the rails at the same time by assigning the same STROBE to rails in PWR_SEQ0
register, rails will be staggered in a manner that a subsequent rail
’s enable is gated by PG of a preceding
rail. In this case, the default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and
CP1(VDDH). If any two PWRx pins are pulled low together or the sequencer tries to bring down the rails at
the same time by assigning the same STROBE to rails in PWR_SEQ0 register, then all rails will go down at
the same time.
2010–2011, Texas Instruments Incorporated
13
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| TPS65182RGZR | 功能描述:LCD Gamma缓冲器 Pwr Mgt IC for E Ink Vizplex RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
| TPS65182RGZT | 功能描述:LCD Gamma缓冲器 Pwr Mgt IC for E Ink Vizplex RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
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