- 您现在的位置：买卖IC网 > PDF目录199467 > TPS65181RGZR (TEXAS INSTRUMENTS INC) POWER SUPPLY MANAGEMENT CKT, PQCC48 PDF资料下载
参数资料
| 型号： | TPS65181RGZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQCC48 |
| 封装： | 7 X 7 MM, 0.90 MM HEIGHT, GREEN, PLASTIC, VQFN-48 |
| 文件页数： | 8/41页 |
| 文件大小： | 892K |
| 代理商： | TPS65181RGZR |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
SLVSA76F
– MARCH 2010 – REVISED FEBRUARY 2011
Whenver
the
TPS65180/TPS65181
and
TPS65180B/TPS65181B
encounter
under
voltage
on
VNEG
(VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV) or VDDH (VDDH_UV) it will shut down the corresponding rail
(plus any dependent rail) only and remain in ACTIVE mode, allowing the DCDC converters to remain up. Again,
the PWR_GOOD and nINT pins will be pulled low and the corresponding interrupt bit will be set.
TPS65180/TPS65180B FAULT HANDLING
Once a fault is detected the TPS65180/TPS65180B sets the appropriate interrupt flags in the INT_STATUS1 and
INT_STATUS2 registers and pulls INT pin low to signal an interrupt to the host processor. None of the power
rails can be re-enabled before the host has read the INT_STATUSx bits and the fault has been removed. As the
PWRx inputs are edge sensitive, the host must also toggle the PWRx pins to re-enable the rails through GPIO
control, i.e. it must bring the PWRx pins low before asserting them again.
TPS65181/TPS65181B FAULT HANDLING
The TPS65181/TPS65181does not require the host processor to access the INT_STATUS registers before
re-enabling the output rails. Rails can be re-enabled as soon as the fault condition has been removed. Again, as
the PWRx inputs are edge sensitive, the host must also toggle the PWRx pins to re-enable the rails through
GPIO control, i.e. it must bring the PWRx pins low before asserting them again.
POWER GOOD PIN
The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1,
CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains
low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released
to HiZ state (pulled up by external resistor).
INTERRUPT PIN
The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT_STATUS1 or
INT_STATUS2 bits are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the
register with the set bit has been read by the host. If the fault persists, the INT_pin will be pulled low again after a
maximum of 32
s.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_ENABLE1 and
INT_ENABLE2 register, i.e. the user can determine which events cause the nINT pin to be pulled low. The status
of the enable bits affects the nINT pin only and has no effect on any of the protection and monitoring circuits or
the INT_STATUSx bits themselves.
Note that persisting fault conditions such as thermal shutdown can cause the nINT pin to be pulled low for an
extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not
desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT_STATUSx register
to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
PANEL TEMPERATURE MONITORING
The TPS65180/TPS65181 and TPS65180B/TPS65181B provide circuitry to bias and measure an external
negative temperature coefficient resistor (NTC) to monitor device temperature in a range from
–10°C to 85°C
with and accuracy of
±1°C from 0°C to 50°C. The TPS65180/TPS65180B requires the host to trigger the
temperature acquisition through an I2C command whereas the TPS65181/TPS65181B triggers the temperature
acquisition automatically once every 60 s.
NTC BIAS CIRCUIT
Figure 5 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-k
Ω bias resistor. A 43-kΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-k
Ω NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two
’s complement by digital per Table 1.
16
2010–2011, Texas Instruments Incorporated
相关PDF资料 |
PDF描述 |
|---|---|
| TPS721A | FIBER OPTIC PHOTODIODE DETECTOR, THROUGH HOLE MOUNT |
| TPS793285DBVRQ1 | 2.85 V FIXED POSITIVE LDO REGULATOR, 0.2 V DROPOUT, PDSO5 |
| TPSMA11A/5A | 400 W, UNIDIRECTIONAL, SILICON, TVS DIODE, DO-214AC |
| TPSMA15A/5A | 400 W, UNIDIRECTIONAL, SILICON, TVS DIODE, DO-214AC |
| TPSMB33/5 | 600 W, UNIDIRECTIONAL, SILICON, TVS DIODE, DO-214AA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TPS65181RGZT | 功能描述:LCD Gamma缓冲器 Pwr Mgmt IC for Elec Paper Display RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
| TPS65182BRGZR | 功能描述:LCD Gamma缓冲器 PMIC for E Ink Vizplex RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
| TPS65182BRGZT | 功能描述:LCD Gamma缓冲器 PMIC for E Ink Vizplex RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
| TPS65182RGZR | 功能描述:LCD Gamma缓冲器 Pwr Mgt IC for E Ink Vizplex RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
| TPS65182RGZT | 功能描述:LCD Gamma缓冲器 Pwr Mgt IC for E Ink Vizplex RoHS:否 制造商:Maxim Integrated 输入补偿电压: 转换速度: 电源电压-最大:20 V 电源电压-最小:9 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-38 封装:Tube |
发布紧急采购，3分钟左右您将得到回复。