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参数资料
| 型号： | TS-MAC-E2-U4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 2/66页 |
| 文件大小： | 0K |
| 描述： | IP CORE ETH MAC TRI-SPEED EC/ECP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACE2U4 |
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Table of Contents
Chapter 1. Introduction .......................................................................................................................... 5
Quick Facts ........................................................................................................................................................... 5
Features ................................................................................................................................................................ 6
Chapter 2. Functional Description ........................................................................................................ 7
Configuration Options ........................................................................................................................................... 7
Classic TSMAC Option ................................................................................................................................ 7
1G or SGMII Configurable Options .............................................................................................................. 8
Functional Overview.............................................................................................................................................. 9
System Block Diagrams ...................................................................................................................................... 11
Core Signal Descriptions..................................................................................................................................... 14
Host Interface............................................................................................................................................. 19
Receive MAC (Rx MAC) ............................................................................................................................ 19
Transmit MAC (Tx MAC)............................................................................................................................ 22
Internal Data Buffer and FIFO Interfaces ................................................................................................... 24
(Optional) Media Independent Interface Management Module (MIIM) ...................................................... 24
Internal Registers ................................................................................................................................................ 25
Register Descriptions .......................................................................................................................................... 26
MODE (R/W) .............................................................................................................................................. 26
Transmit and Receive Control (R/W) ......................................................................................................... 27
Maximum Packet Size (R/W) ..................................................................................................................... 27
IPG (Inter-Packet Gap) (R/W) .................................................................................................................... 27
MAC Address Register {0,1,2} (R/W), Set of Three ................................................................................... 28
Transmit and Receive Status (RO) ............................................................................................................ 28
VLAN Tag (RO).......................................................................................................................................... 28
GMII Management Register Access Control (R/W) ................................................................................... 29
GMII Management Access Data (R/W)...................................................................................................... 29
Multicast Tables (R/W), Set of Eight .......................................................................................................... 29
Pause Opcode (R/W) ................................................................................................................................. 30
Timing Specifications .......................................................................................................................................... 30
Reception of a 64-Byte Frame Without Error -Rx MAC Application Interface............................................ 30
Reception of a 64-byte Frame with Error(s) - Rx MAC Application Interface............................................. 31
Reception of a 64-Byte Frame with FIFO Overflow - Rx MAC Application Interface ................................. 31
Successful Transmission of a 64-Byte Frame -Tx MAC Application Interface........................................... 32
Successful Transmission of a 64-byte Frame with FIFO Empty - Tx MAC Application Interface .............. 33
Aborted Transmission Due to FIFO Empty - Tx MAC Application Interface .............................................. 34
Reception and Transmission of 64-byte Frames With SGMII Easy Connect Option ................................. 34
Host Interface Read/Write Operation .................................................................................................................. 35
Management Interface Read/Write Operation .................................................................................................... 36
GMII Transmit and Receive Operations (1G mode and Gigabit MAC Option)........................................... 36
MII Transmit and Receive Operations (10/100 Mode) ............................................................................... 37
Chapter 3. Parameter Settings ............................................................................................................ 38
TSMAC Configuration Dialog Box....................................................................................................................... 38
Parameter Descriptions....................................................................................................................................... 38
MIIM_MODULE.......................................................................................................................................... 38
Operation Mode ......................................................................................................................................... 38
Synthesis/Simulation Tools Selection ........................................................................................................ 39
Chapter 4. IP Core Generation and Evaluation .................................................................................. 40
Licensing the IP Core.......................................................................................................................................... 40
Getting Started .................................................................................................................................................... 40
? 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG51_03.0, December 2010
2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TS-MAC-E2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-E3-U3 | 功能描述:开发软件 Tri-Speed ethernet MAC RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-E3-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-E3-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACP2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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