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参数资料
| 型号： | TSB43AA82PGE |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 54/146页 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
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15
1.4.2
Microcontroller/Microprocessor Signals
TERMINAL
I/O
DESCRIPTION
NAME
PGE NO.
GGW NO.
I/O
DESCRIPTION
ALE
82
M15
I
Address latch enable. Ignored when not DA mux mode
(MUXMODE = 1).
DA[15:0]
76, 74, 73, 72,
71, 69, 68, 65,
64, 62, 61, 60,
58, 57, 56, 55
P15, R16, T17,
U16, T15, R14,
U14, R12, T12,
R11, T11, U11,
T10, U10, T9,
R9
I/O
I/O lines used for address and data. See Table 21 for more information on the
use of address and data lines.
M8M16
5
D1
I
Bit width select. M8M16 determines the width of the data bus. The terminal is tied
high for 16 bit mode. See Table 21 for more information on the use of address
and data lines.
MUXMODE
6
E3
I
Mode selects. MUXMODE determines if the data and address lines are parallel
or multiplexed. The terminal is tied high for data address multiplex mode. See
Table 21 for more information on the use of address and data lines.
XCS
84
M17
I
Chip select
XINT
54
U9
O
Interrupt
XRD
78
P17
I
Read cycle enable
XWAIT
77
P16
O
Wait
XWR
81
N17
I
Write cycle enable
1.4.3
Physical Layer
TERMINAL
I/O
DESCRIPTION
NAME
PGE NO.
GGW NO.
I/O
DESCRIPTION
CNA
135
C6
O
Cable not active output. If no bias is detected from the cable, the CNA signal is set high.
The CNA output is not valid during power-up reset. CNA is valid during power-down
mode, when PD is high.
CONTEND
139
A4
I
Contend. Tie high for bus manager capability.
CPS
142
A3
I
Cable power supply. This terminal is normally connected to cable power through a
400-k
resistor. This circuit drives an internal comparator that is used to detect the
presence of cable power.
FILTER0
FILTER1
111
112
A15
A14
I
PLL filter. These terminals are connected to an external capacitor to form a lag-lead
filter required for stable operation of the internal frequency multiplier PLL running off the
crystal oscillator. A 0.1-
F ±10% capacitor is the only external component required to
complete this filter.
LINKON
138
C5
O
Link-on. The link-on output is activated if the LLC is inactive (LPS inactive or PD active).
The signal indicates that the PHY has detected a link-on packet addressed to this node,
or has detected a resume event on a suspended port. The signal remains asserted until
the LPS signal is asserted by the link in response.
LPS
130
A7
I
Link power status. The signal indicates that the link is powered up and ready for trans-
actions. When this mode is deasserted, the device can be put into a low power mode.
PD
136
A5
I
Power-down input. When PD is asserted, the device is in a power-down mode. The
device is asynchronously reset during this mode, so a device reset must be provided
after PD is deasserted. See Section 12 for more details.
PWRCLS[2:0]
134, 133,
132
B6, A6, C7
I
Power class inputs. See 1394a-2000 for more information. On hardware reset, these
inputs set the default value on the power class indicated during self-ID. Programming is
done by tying terminals high or low.
R0
R1
99
100
F17
F16
—
Current setting resistor terminals. An external resistor is connected between these
terminals to set the internal operating currents and cable driver output currents. A
resistance of 6.34 k
±1.0% is required to meet the IEEE Std 1394-1995 output voltage
limits.
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